Method and system for optimal diameter bounding of designs with complex feed-forward components

Abstract

A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for the netlist comprising at least one SCC, where the additive diameter includes a fanin additive diameter determined based on a propagation delay difference of the at least two input paths to a SCC and a number of complex feed-forward components within at least one input path. In response to the reconvergent fanin input to the SCC providing a binate function, the method computes a multiplicative diameter for the SCC utilizing a least common multiple (LCM) derived from one or more propagation delay differences across each reconvergent fanin input leading to the SCC.

Description

BACKGROUND[0001]1. Technical Field[0002]The present disclosure generally relates to verification techniques for logic design and in particular to techniques for performing diameter bounding for complex feed-forward components in a logic design.[0003]2. Description of the Related Art[0004]Design verification refers to the process of establishing the correctness of a given logic design. Due to the complexity of modern logic designs, formal verification methods are gaining widespread use to augment the coverage shortcomings of simulation-based validation approaches. Formal verification methods are exhaustive, and thus are guaranteed to expose all possible logic flaws. In contrast, simulation-based validation is incomplete, and thus may fail to expose certain logic flaws (or bugs). While formal verification is a very powerful technology, formal verification generally requires exponential resources with respect to design size and thus is often only applicable to smaller design components...

AI Technical Summary

Problems solved by technology

Formal verification methods are exhaustive, and thus are guaranteed to expose all possible logic flaws.

In contrast, simulation-based validation is incomplete, and thus may fail to expose certain logic flaws (or bugs).

While formal verification is a very powerful technology, formal verification generally requires exponential resources with respect to design size and thus is often only applicable to smaller design components.

For example, symbolic simulation techniques exhaustively analyze design behavior for a specific number of bounded time-frames.

However, the bounded nature of this approach implies incompleteness.

Unfortunately, techniques to tightly estimate design diameter are generally as complex as the process of verification itself.

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