Method of replacing silicon with metal in integrated circuit chip fabrication

Abstract

A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and / or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]The present invention is a divisional of U.S. application Ser. No. 13 / 310,796 (Attorney Docket No. YOR920110478US1) “METHOD OF REPLACING SILICON WITH METAL IN INTEGRATED CIRCUIT CHIP FABRICATION” to Kevin K. Chan et al., filed Dec. 5, 2011, assigned to the assignee of the present invention and incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to reducing costs in semiconductor chip manufacture of integrated circuits with Field Effect Transistors (FETs) with metal gates and / or metal contacts.[0004]2. Background Description[0005]A primary goal in integrated circuit (IC) chip manufacturing is increasing chip density and performance, i.e., placing more function that operates at higher speeds. To achieve that goal, semiconductor technology and chip manufacturing advances have steadily decreased chip...

AI Technical Summary

Benefits of technology

The patent aims to address three technical problems in ICs: reducing short channel effects without affecting performance, improving replacement metal gate FET chip reliability and quality, and improving replacement metal contact reliability and quality. Additionally, it aims to reduce pinch off in replacement metal contacts.

Problems solved by technology

Thus, notwithstanding the decrease of chip supply voltage, chip power consumption has increased as well.

At both chip level and system level, cooling and packaging costs have escalated as a natural result of this increase in chip power.

However, since improving performance means running circuits faster (with higher switching speeds), reducing chip power consumption is at odds with improving performance.

In practice, however, typical FETs are much more complex than switches.

Especially for complex chips and arrays with a large number of devices, short channel effects can be overwhelming.

When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA).

Unfortunately, however, polysilicon cannot be used with high-k dielectrics.

This strain causes these narrow aspect ratio trenches to buckle and partially collapse, such that frequently the top of some trenches close (pinch off).

Even in those metal gates that form with voids, the voids can introduce resistance or act as a dielectric above the high-k dielectric, randomly altering device characteristics unintentionally.

Missing contacts can cause a circuit and chip failure, i.e., yield loss.

This random resistance can cause erratic failures that are difficult to identify and may not manifest until a chip is in place in the field.

These missing contacts and contact voids raise manufacturing costs and degrade chip quality, making it difficult to reliably make consistent structures.

Consequently, trench aspect ratio has been a limit both on reducing RMG device length and on increasing contact density.

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