Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The present application claims priority to Korean patent application number 10-2012-0089571, filed on 16 Aug. 2012, which is incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]1. Technical Field[0003]The present invention relates to a semiconductor device and a method for manufacturing the same.[0004]2. Related Art[0005]Stacking technology to form a three-dimensional (3D) semiconductor integrated circuit (IC) has been developed to reduce the size of electronic appliances, increase stack density, and improve performance. The 3D stack package is a package in which a plurality of chips each having the same storage capacity are stacked, and is generally referred to as a stack chip package.[0006]A stack chip package reduces fabrication costs using a simplified manufacturing process and enables mass production. However, a highly integrated stack chip package also has reduced interconnection space for electrical connectio...

AI Technical Summary

Benefits of technology

The patent text describes a way to increase the yield of semiconductor devices and reduce the likelihood of cracks occurring during a process. This is done by improving the process parameters so that the bottom of a TSV (a type of structure used in semiconductor devices) is not exposed. By doing this, semiconductor devices can be made more efficiently and with fewer defects.

Problems solved by technology

However, a highly integrated stack chip package also has reduced interconnection space for electrical connections between chips.

However, in that case, the heights of the TSVs protruding out of the back surface of the wafer increases, causing device failures.

On the other hand, if the rear surface of the wafer is excessively etched to expose the shallower TSVs, the wafer becomes thin and thus becomes vulnerable to cracks.

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