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Method of fabricating semiconductor package

a technology of semiconductor packaging and semiconductor components, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical equipment, etc., to achieve the effect of improving process speed and reducing costs

Inactive Publication Date: 2014-08-28
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a way to make semiconductor packages faster and cheaper.

Problems solved by technology

One of the major challenges in the semiconductor industry is to fabricate small, multi-function, high-capacity and highly reliable products at low costs.

Method used

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  • Method of fabricating semiconductor package
  • Method of fabricating semiconductor package
  • Method of fabricating semiconductor package

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Embodiment Construction

[0023]Features and utilities of the present inventive concept and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The present inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the inventive concept to those skilled in the art, and the present inventive concept will only be defined by the appended claims. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0024]It will be understood that when an element or layer is referred to as being “on” or “connected to” another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. In contras...

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Abstract

A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority from Korean Patent Application No. 10-2013-0020632 filed on Feb. 26, 2013 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present inventive concept relates to a method of fabricating a semiconductor package.[0004]2. Description of the Related Art[0005]One of the major challenges in the semiconductor industry is to fabricate small, multi-function, high-capacity and highly reliable products at low costs. One of the most important technologies that make it possible to achieve such a complex goal is semiconductor package technology. Of package technologies, a chip-stacked semiconductor package in which a plurality of chips are stacked is being suggested as a way to achieve the above complex goal.SUMMARY OF THE INVENTION[0006]Features of the present inventive concept provid...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/00
CPCH01L24/95H01L21/486H01L21/56H01L21/76898H01L23/3128H01L23/3135H01L23/49827H01L24/81H01L24/94H01L24/97H01L2224/16145H01L2224/16225H01L2224/16227H01L2224/32145H01L2224/32225H01L2224/73204H01L2224/94H01L2224/97H01L2924/12042H01L2924/15311H01L2924/18161H01L2924/00H01L2224/81H01L2224/83H01L23/48H01L21/76897H01L21/78H01L24/11H01L25/50H01L2224/1182H01L2224/13024H01L2224/16235
Inventor PARK, JAE-YONGKO, JUN-YOUNGKIM, SANG-JUN
Owner SAMSUNG ELECTRONICS CO LTD