Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods

a vector processing engine and data path configuration technology, applied in digital computers, instruments, climate sustainability, etc., can solve the problems of increasing the execution time of vector instruction, consuming additional power, etc., and achieve the effect of saving the area of the baseband processor, fewer register writes, and faster instruction execution

Active Publication Date: 2014-09-18
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0013]As a result, fewer VPEs can provide desired technology specific, thus saving area in the baseband processor while still retaining vector processing advantages of fewer register writes and faster instruction execution compared to scalar processing engines. The data path configurations for the vector processing blocks may also be programmed and reprogrammed during vector instruction execution in the VPE to support execution of different, specialized vector operations in different modes in the VPE.
[0014]The VPEs having programmable data path configurations for multi-mode vector processing disclosed herein are distinguishable from VPEs that only include fixed data path configurations to provide fixed functions. The VPEs having programmable data path configurations for vector processing disclosed herein are also distinguishable from scalar processing engines, such as those provided in digital signal processors (DSPs) for example. Scalar processing engines employ flexible, common circuitry and logic to perform different types of non-fixed functions, but also write intermediate results during vector instruction execution to register files, thereby consuming additional power and increasing vector instruction execution times.

Problems solved by technology

Scalar processing engines employ flexible, common circuitry and logic to perform different types of non-fixed functions, but also write intermediate results during vector instruction execution to register files, thereby consuming additional power and increasing vector instruction execution times.

Method used

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  • Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods
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  • Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods

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Embodiment Construction

[0032]With reference now to the drawing figures, several exemplary embodiments of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0033]Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include at least one vector processing stage configured to process vector data according to a vector instruction being executed by a vector processing stage. Each vector processing stage includes one or more vector processing blocks configured to process vector data based on the vector instruction being executed. Non-limiting examples of vector processing blocks are multipliers and acc...

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Abstract

Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed.

Description

RELATED APPLICATIONS[0001]The present application is related to U.S. patent application Ser. No. 13 / 798,599 (Qualcomm Docket No. 123247) entitled “Vector Processing Engines Having Programmable Data Path Configurations For Providing Multi-Mode Radix-2X Butterfly Vector Processing Circuits, And Related Vector Processors, Systems, And Methods,” filed on Mar. 13, 2013 and incorporated herein by reference in its entirety.[0002]The present application is also related to U.S. patent application Ser. No. 13 / 798,618 (Qualcomm Docket No. 123248) entitled “Vector Processing Carry-Save Accumulators Employing Redundant Carry-Save Format To Reduce Carry Propagation, And Related Vector Processors, Systems, And Methods,” filed on Mar. 13, 2013 and incorporated herein by reference in its entirety.BACKGROUND[0003]I. Field of the Disclosure[0004]The field of the disclosure relates to vector processors and related systems for processing vector and scalar operations, including single instruction, multip...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F9/30
CPCG06F9/30036G06F9/3887G06F9/3897G06F15/7867G06F15/8053Y02D10/00
Inventor KHAN, RAHEEL
Owner QUALCOMM INC
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