Method of fabricating a non-volatile memory

Abstract

A structure of a memory cell includes a substrate, a well, two source / drain doped regions, a stacked layer and a metal gate. The stacked layer includes a tunneling layer, and a charge trapping layer. A method of fabricating the memory cell may vary with the change in sequence of performing steps. The difference in sequence of fabrication may yield different characteristic variations for the formed components of the memory cell.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This non-provisional application claims priority of US provisional application U.S. 61 / 883,205 filed on Sep. 27, 2013.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a non-volatile memory cell, and more specifically, to a non-volatile memory cell having a metal gate and a method of fabricating the non-volatile memory cell.[0004]2. Description of the Prior Art[0005]Non-volatile memory can store data in the absence of a power supply, therefore it is preferred to be used by various portable electronic products such as personal digital assistants (PDAs), mobile phones, and memory cards. In order to respond to the requirements of the market, non-volatile memory technology must have compatibility with CMOS processing, low power consumption, high writing efficiency, low cost, and high density. However, as non-volatile memory becomes smaller in size, the gate oxide layer becomes accordingly thinner...

AI Technical Summary

Benefits of technology

The present invention provides a method of making a memory cell by forming isolations on a substrate, creating a well in the substrate, adding a tunneling layer and a charge trapping layer on top of the well, adding a high-k gate dielectric layer on top of the tunneling layer, adding a poly silicon gate on top of the high-k gate dielectric layer, adding at least two source / drain doped regions on the well, removing the poly silicon gate, adding a stacked layer comprising a tunneling layer and a charge trapping layer on top of the removed area of the poly silicon gate, adding a metal gate on top of the high-k gate dielectric layer. This method creates a memory cell with improved performance and reliability.

Problems solved by technology

However, as non-volatile memory becomes smaller in size, the gate oxide layer becomes accordingly thinner making stored data dissipate easily and causes a problem in the data storing ability.

And as the gate length becomes smaller, the greater a problem the gate leakage power becomes.

In fabricating a stacked gate memory cell using an advance replacement metal gate process, problems may be encountered with regard to fitting the fabrication process of the stacked gate memory cell into the advance replacement metal gate process.

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