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Random access memory and method of adjusting read timing thereof

a random access memory and read timing technology, applied in the field of random access memories, can solve problems such as missing an opportunity for improving operation

Active Publication Date: 2015-04-30
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The invention is about adjusting the timing when reading data from random access memories. The technical effect is to improve the speed and accuracy of reading data from these memories.

Problems solved by technology

In conventional art, the output timing of the column select signal is not flexible, thus missing an opportunity for improving operation of Read data-path transmission or operation of bit-line for the random access memory.

Method used

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  • Random access memory and method of adjusting read timing thereof
  • Random access memory and method of adjusting read timing thereof
  • Random access memory and method of adjusting read timing thereof

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Embodiment Construction

[0011]The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims

[0012]The disclosure provides a random access memory that adjusts read timing dynamically and a method thereof. FIG. 1 schematically shows a block diagram of a random access memory circuit 100 in an exemplary embodiment of the disclosure. The random access memory circuit 100 comprises a command decoder 120, a shift calculating circuit 140 and a column enable circuit 160.

[0013]The command decoder 120 controls access operation of the random access memory 100. The command decoder 120 receives input signals (IP) and decodes them into corresponding access commands respectively such as active command (ACT), write command (WT), read command (RD) and a mode register command (MR...

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Abstract

A method of adjusting read timing of a random access memory. The method includes providing a Column Address Strobe (CAS) value for defining an CAS latency (CL) of the random access memory; generating a shift margin according to the CAS latency and a reference latency; generating a read command for accessing the random access memory; dynamically generating a Column Select (CS) signal and adjusting output timing of the CS signal according to the shift margin, after the read command is generated.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to random access memories, and in particular relates to a method of adjusting read timing of random access memories.[0003]2. Description of the Related Art[0004]The access time of a random access memory (RAM) is a crucial factor for improving the performance and speed of an electronic system. The RAS (Row Address Strobe) to CAS (Column Address Strobe) latency is a delay time between an active command and a read command sent from a command decoder in a random access memory, and CAS (Column Address Strobe) latency is a delay time between the time the read command is sent and the time the memory data is ready to be read out at a data bus. After the read command is sent, a column select signal is subsequently (later than the read command being output for a predetermined time) output by a column enable circuit in the random access memory. In conventional art, the output timing of the column sele...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G11C7/22
CPCG11C7/222G11C7/1066G11C2207/2272G11C7/22G11C11/4076G11C8/18
Inventor WU, SHUN-KER
Owner NAN YA TECH