Method for producing integrated circuit memory cells with less dedicated lithographic steps

Abstract

Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Description

TECHNICAL FIELD[0001]The technical field generally relates to methods of producing integrated circuits having memory cells, and more particularly relates to low cost methods of producing integrated circuits having memory cells.BACKGROUND[0002]Embedded super flash memory cells are used in certain integrated circuits, where the embedded super flash memory cells can be erased and re-programmed. There are at least three generations of super flash memory cells, where each generation is smaller than the previous. The third generation memory cells include a stack with a control gate overlaying a control gate dielectric that in turn overlies a floating gate, where the floating gate overlies a floating gate dielectric. The entire stack overlies a substrate.[0003]Many processes are included in the production of such integrated circuits, such as lithography, etching and deposition. Lithography involves the deposition of a photoresist layer followed by patterning of that photoresist layer. The ...

AI Technical Summary

Benefits of technology

[0007]A method of producing an integrated circuit is provided in yet another embodiment. The method includes patterning a source line photoresist mask to overlie a drain line area while exposing a source line area within an active section of the integrated circuit, where the source line photoresist mask overlies the source line area in a strap section. The source line area is defined within a substrate between first and second memory cells, and the drain line area is defined within the substrate between second and third memory cells. A source line is formed in the source line area within the active section of the integrated circuit. A source line dielectric is concurrently formed with a drain line dielectric, where the source line dielectric overlies the source line area and the drain line dielectric overlies the drain line area. A drain line photoresist mask is patterned to overlie the source line in the active section while exposing the source line area in the strap section, and where the drain line photoresist mask exposes the drain line area in both the active and strap sections of the integrated circuit. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced. An interlayer dielectric is formed overlying the source line area and the drain line area, and a contact is formed in electrical communication with the source line area in the strap section.

Problems solved by technology

Lithography techniques are expensive, so integrated circuit production techniques that include more lithography processes tend to be more expensive than those with fewer lithography processes.

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