Method to improve latency in an ethernet phy device

Abstract

This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

Description

FIELD OF THE DISCLOSURE[0001]This document relates to electronic circuits for data communication networks. Some embodiments relate to circuits that improve the process of encoding and decoding data communicated using a data communication network.BACKGROUND[0002]Ethernet networks are widely used in industry. Some aspects of Ethernet networks are standardized by the Institute Electrical and Electronic Engineers (IEEE) 802.3 standard. Implementations of Ethernet networks can include communication or processing nodes joined by twisted pair cable as the physical network medium. The interface circuitry of a node to the network medium can be referred to as the physical layer or PHY layer of the node. A gigabit Ethernet PHY layer may employ many signal processing techniques to attain the performance required to implement the different aspects of the IEEE 802.3 standard. In an industrial Ethernet implementation, latency of communication speed can become a limiting factor as Ethernet systems ...

AI Technical Summary

Benefits of technology

[0003]This document relates generally to data communication networks, and in particular to reducing latency due to decoding data received over a data communication network. In some embodiments, physical (PHY) layer circuitry of a data communication apparatus includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives data via a network link. The received data includes data symbols plus additive noise due to the network link. The data symbols may be encoded at the transmit source using trellis coded modulation (TCM). The decoder circuitry decodes the data symbols using a maximum-likelihood (ML) decoding method to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. The trace-back depth value is a number of symbols of delay introduced by the ML decoding in identifying the most likely allowed symbol sequence. The more delay that is introduced, the more reliable the decoding decisions that are made by the decoder circuitry. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

Problems solved by technology

In an industrial Ethernet implementation, latency of communication speed can become a limiting factor as Ethernet systems strive for improved performance and scale.

Images