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Semiconductor device and method for fabricating the same

a semiconductor and semiconductor technology, applied in the direction of semiconductor devices, electrical devices, transistors, etc., can solve the problems of higher cost and performance suffer

Active Publication Date: 2020-01-23
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In radio frequency (RF) integrated circuit application, such as RF switch device or power amplifier device, performance is suffered from “parasitic surface charge” issue, which in turn generates harmonic effect.
However, the utilization of SOI wafer or substrate in current process usually results in higher cost.

Method used

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  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same

Examples

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Embodiment Construction

[0008]Referring to FIGS. 1-7, FIGS. 1-7 illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12, such as a silicon-on-insulator (SOI) substrate is provided, in which the substrate 12 preferably includes a first semiconductor layer 14, an insulating layer 16 on the first semiconductor layer 14, and a second semiconductor layer 18 on the insulating layer 16. Preferably, the first semiconductor layer 14 and the second semiconductor layer 18 could be made of same material or different material and could both be made of material including but not limited to for example silicon, germanium, or silicon germanium (SiGe). The insulating layer 16 disposed between the first semiconductor layer 14 and the second semiconductor layer 18 preferably includes SiO2, but not limited thereto. Preferably, an additional trap rich layer 20 is disposed between the first semiconductor layer 14 and the insulating layer ...

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Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first silicon layer, an insulating layer on the first silicon layer, and a second silicon layer on the insulating layer; forming a metal-oxide semiconductor (MOS) transistor on the substrate; forming an interlayer dielectric layer (ILD) on the MOS transistor; removing part of the ILD layer to form a first trench to expose the insulating layer; and performing a wet etching process through the first trench to remove part of the insulating layer for forming a first air gap under the MOS transistor.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The invention relates to a method for fabricating semiconductor device, and more particularly to a method of forming air gap under active device for reducing capacitance of the device.2. Description of the Prior Art[0002]In radio frequency (RF) integrated circuit application, such as RF switch device or power amplifier device, performance is suffered from “parasitic surface charge” issue, which in turn generates harmonic effect. There are several wafer process technologies available for solving the issue such as using semiconductor-on-insulator (SOI) wafer to isolate the charges from the high resistivity wafer substrate. However, the utilization of SOI wafer or substrate in current process usually results in higher cost. Hence how to improve the performance of current process while finding a more effective way to lower cost has become an important task in this field.SUMMARY OF THE INVENTION[0003]According to an embodiment of ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L29/786H01L29/06H01L29/66H01L21/311H01L21/764
CPCH01L29/66742H01L29/7841H01L21/31111H01L21/764H01L29/78603H01L29/0649H01L29/0688H01L29/0642H01L29/66409H01L29/78H01L29/66772H01L29/78654H01L21/84H01L21/76232H01L21/76264
Inventor VERMA, PURAKH RAJSU, CHIH-WEIWEN, JE-MIN
Owner UNITED MICROELECTRONICS CORP