Method for generating redundant configuration in fpgas
Active Publication Date: 2020-08-20
UNIV DEGLI STUDI DI NAPOLI FEDERICO II
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However, these devices are sensitive to radiation effects such as single event upsets (SEUs) or multiple bit upsets (MBUs) in the configuration memory, which may alter the implemented functionality as disclosed in M. Wirthlin, “High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond”, in Proc. of the IEEE, vol.
DS192 (v1.4) Nov. 12, 2014) have been designed for space applications, but their high cost (few 10 k$), with respect to their standard counterpart (˜500$), usually limits their usage in other applications, including the control of particle accelerators, medical applications or electronics for Nuclear and Sub-Nuclear Physics experiments.
These circuitries normally are limited by the amount of parity bits in the maximum number of errors they can detect and correct.
Being external components, these memories add up to the overall system complexity, cost and power consumption.
Since it requires a dedicated FPGA architecture, this approach can be pursued only by vendors fabricating devices and it cannot be implemented at the user level.
Moreover, it does not allow to detect upsets, but only to mask them, therefore it is not effective against the accumulation of upsets and it does not allow to log them.
The main limitations of this approach are the need for three devices, the increase of the power consumption by a factor three and the need for an additional device or resources to perform scrubbing and majority voting of the outputs.
The disclosed solution requires to find three identical subsets of the FPGA device for hosting the three identical layouts, which may not be possible for designs occupying a higher percentage of the device resources.
This solution leads to a power consumption increase related to the additional programmable resources used.
Unfortunately, newer FPGA families, such as the 7-Series, the Ultrascale or the Ultrascale+, are not supported by the Rapidsmith tool, and latest generation FPGAs are not supported by ISE either.
In addition to that, the new Xilinx® CAD tool Vivado, recommended for designs based on 7-Series onwards, does not support the XDL.
However, the usage of third party layout tools adds up to the complexity of the design flow and it usually does not allow the designer to choose the latest generation devices, since dedicated support must be implemented for each new FPGA family.
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[0046]In this description, any reference to “an embodiment” will indicate that a particular configuration, structure or feature described in regard to the implementation of the invention is comprised in at least one embodiment. Therefore, the phrase “in an embodiment” and other similar phrases, which may be present in different parts of this description, will not necessarily be all related to the same embodiment. Furthermore, any particular configuration, structure or feature may be combined in one or more embodiments in any way deemed appropriate.
[0047]The references below are therefore used only for the sake of simplicity, and do not limit the protection scope or extension of the various embodiments.
[0048]All user-programmable features of FPGA devices are controlled by memory cells, which must be configured according to the design to be implemented.
[0049]These memory cells are collectively known as configuration memory, as disclosed in “7-Series FPGAs Configuration User Guide”, Xi...
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A method for generating redundant configuration in FPGA devices includes: analysing the configuration pertaining to a given design to be configured, or already configured, in the FPGA device, in order to identify programmed and empty configuration memory portions, configuring the FPGA device for implementing said design, measuring the power consumption of the configured FPGA device, copying the configuration from at least some subsets of the programmed portion to subsets of the empty portion, (a) verifying the configuration read back from said subsets of the empty portion with the configuration data read from said subsets of the programmed portion, (b) verifying whether the functionality of the design after the copy is still correct, (c) measuring the power consumption of the FPGA device, and verifying whether the power consumption of the FPGA device after the copy is acceptable according to pre-defined criteria, if the verification steps (a), (b) and (c) are all successful the redundant configuration is correctly generated, and if the verification steps (a), (b) and (c) are not all successful the method restarts from the beginning choosing other subsets of the empty portion of the FPGA device for hosting the configuration data from said subsets of the programmed portion.
Description
BACKGROUND OF THE INVENTIONField of the Invention[0001]The present invention generally relates to Field Programmable Gate Arrays (FPGAs) and more particularly to techniques for generating redundant configuration within those FPGA devices. The redundant configuration can be exploited by properly-devised circuits for detecting and correcting upsets in the configuration memory and mitigating their effects on the implemented functionality.Description of the Prior Art[0002]FPGAs are integrated circuits that may be programmed to perform specific logic functions, as disclosed in “Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics”, Xilinx Inc. DS893 (v1.7.1) Apr. 4, 2016 and “Stratix 10 Device Overview S10-OVERVIEW”, Altera Corp. 2015 Dec. 4.[0003]These integrated circuits typically consist of an array of programmable resources. These programmable resources can include dedicated input and output blocks (IOBs) and configurable logic blocks (CLBs), random access memory b...
Claims
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Login to View More IPC IPC(8): G06F30/331G06F30/337G06F30/34
CPCG06F30/337G06F30/331G06F30/34H03K19/17768G01R31/31816G06F30/343G06F30/347G06F2119/06H03K19/177
InventorGIORDANO, RAFFAELE
OwnerUNIV DEGLI STUDI DI NAPOLI FEDERICO II