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Capacitor cluster

a technology of capacitors and clusters, applied in the field of capacitor clusters, can solve the problems of reducing the yield of capacitors that may be manufactured from wafer semiconductor substrates, affecting the ability to reduce and affecting the ability to manufacture capacitors. the effect of reducing the cost of capacitors

Active Publication Date: 2021-01-28
MURATA MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a capacitor cluster that helps reduce the cost of manufacturing capacitors. This is achieved by addressing the issue of stress distribution during film formation which can lead to defects in the electrode layer. By reducing the variation in film thickness and shrinkage, the invention prevents cracking or peeling in the electrode layer, resulting in a higher yield of defect-free capacitors. This reduces the cost of manufacturing capacitors and improves the overall efficiency of the process.

Problems solved by technology

When the high stress acts on the electrode layer, cracks or peeling may occur.
The capacitor in which the cracks or the peeling has occurred in the electrode layer becomes a defective product, and thus the yield of the capacitor that may be manufactured from the wafer semiconductor substrate is decreased.
As a result, there is a negative effect in the ability to reduce the cost of the capacitor.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

embodiment 1

[0028]FIG. 1 is a plan view of an example of a capacitor among a plurality of capacitors included in a capacitor cluster according to Embodiment 1 of the present invention when viewed from an outer electrode side. FIG. 2 is a sectional view of the capacitor in FIG. 1 when viewed from a direction of arrows along a line II-II.

[0029]As illustrated in FIG. 1 and FIG. 2, each of a plurality of capacitors 100 included in the capacitor cluster according to Embodiment 1 of the present invention includes a semiconductor substrate 110, a first electrode layer 120, a dielectric layer 130, a second electrode layer 140, and an outer electrode 160. Note that the respective structures and shapes of the first electrode layer 120, the second electrode layer 140, and the outer electrode 160 are not limited to the structures and shapes illustrated in FIG. 1 and FIG. 2.

[0030]The semiconductor substrate 110 has one main surface 111. As illustrated in FIG. 1, the semiconductor substrate 110 has a rectang...

embodiment 2

[0088]Hereinafter, a capacitor cluster according to Embodiment 2 of the present invention will be described. The capacitor cluster according to Embodiment 2 of the present invention differs from the capacitor cluster 500 according to Embodiment 1 of the present invention in that the first capacitor 100F and the second capacitor 100S are different from each other in shape in the first electrode layer 120. Therefore, the description of the configuration similar to that of the capacitor cluster 500 according to Embodiment 1 of the present invention will not be repeated.

[0089]FIG. 15 is a plan view of a capacitor included in the capacitor cluster according to Embodiment 2 of the present invention when viewed from the outer electrode side. In FIG. 15, only a shape of each of the first electrode layer 120 and the second electrode layer 140 is illustrated.

[0090]As illustrated in FIG. 15, in the capacitor according to Embodiment 2 of the present invention, the first electrode layer 120 has ...

embodiment 3

[0101]Hereinafter, a capacitor cluster according to Embodiment 3 of the present invention will be described. The capacitor cluster according to Embodiment 3 of the present invention differs from the capacitor cluster 500 according to Embodiment 1 of the present invention in that the first capacitor 100F and the second capacitor 100S are different from each other in shape in the outer electrode 160. Therefore, the description of the configuration similar to that of the capacitor cluster 500 according to Embodiment 1 of the present invention will not be repeated.

[0102]FIG. 18 is a plan view of a capacitor included in the capacitor cluster according to Embodiment 3 of the present invention when viewed from the outer electrode side. In FIG. 18, the internal structure of the capacitor is not illustrated.

[0103]As illustrated in FIG. 18, in the capacitor according to Embodiment 3 of the present invention, at least one of the outer electrodes 160 has a first region 191b having a rectangular...

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Abstract

A plurality of capacitors and a holding body constructed to hold the plurality of capacitors. Each of the plurality of capacitors includes a semiconductor substrate, a first electrode layer, a dielectric layer, a second electrode layer, and an outer electrode. Among a first capacitor and a second capacitor of the plurality of capacitors, the second capacitor has a shape different from a shape of the first capacitor in at least one of the first electrode layer, the second electrode layer, and the outer electrode.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application is a continuation of International application No. PCT / JP2019 / 015622, filed Apr. 10, 2019, which claims priority to Japanese Patent Application No. 2018-087212, filed Apr. 27, 2018, the entire contents of each of which are incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention relates to a capacitor cluster.BACKGROUND OF THE INVENTION[0003]Japanese Unexamined Patent Application Publication No. 2011-44613 (Patent Document 1) discloses a configuration of a capacitor included in a housing for a plurality of capacitors. The capacitor as an electronic component described in Patent Document 1 includes a circuit element formed on a substrate, an electrode layer connected to the circuit element, a protection layer covering the electrode layer, and a terminal electrode connected to the electrode layer through a via conductor penetrating through the protection layer and provided on the protection ...

Claims

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Application Information

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IPC IPC(8): H01G4/38H01G4/002
CPCH01G4/38H01G4/002H01G4/33H01L28/40
Inventor HARADA, MASATOMITAKEUCHI, MASAKIKAGAWA, TAKESHIMATSUBARA, HIROSHI
Owner MURATA MFG CO LTD