Computer bridge interfaces for accelerated graphics port and peripheral component interconnect devices

Abstract

A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and / or PCI device(s). The core logic chip set has an AGP / PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and / or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Description

1. Field of the InventionThe present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), video graphics processor(s), random access memory and input-output peripherals together, and more particularly, and more particularly, in utilizing a bus bridge(s) in a computer system for dual accelerated graphics ports.2. Description of the Related ArtThis section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.Use of computers, especially personal computers, in business and at home is becoming more and more pervasive because the co...

AI Technical Summary

Benefits of technology

In the AGP 2.times. mode, 8 bytes of data are transferred during each single clock ("CLK") cycle. The AD[31::0] bus is 32 bits or 4 bytes wide, thus, two 4 byte data transfers must be made during each CLK cycle. This is accomplished in the AGP 2.times. mode by using additional source synchronous strobes derived from the AGP clock (CLK). These strobe signals are: AD_STB0 and AD_STB1 which indicate when valid data is present on AD[31::0], and SB_STB which is used in conjunction with the SBA[7::0] signals. These strobe signals allow an effective data transfer rate of eight (8) bytes of data per AGP CLK (66 MHz). In the present invention, separate strobe signals may be used between each AGP connector and the core logic chipset so as not to excessively load down the strobe signals.

Problems solved by technology

Increasingly complex 3-D graphics require higher speed access to ever larger amounts of graphics data stored in memory.

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