Wavefront clock synchronization

Abstract

The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit at the same speed data propagates though the circuit. The cells of the integrated circuit are wavefront clock synchronized in that the phase offset introduced in a particular cell's clock is such that the arrival of a skewed clock and propagation delayed data from that cell's neighbor is synchronized with that particular cell's own clock. Wavefront clock synchronization mitigates at least some of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies associated with large surface integrated circuits utilizing synchronized clock domains.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]The present application is a continuation of U.S. patent application Ser. No. 10 / 330,068, filed Dec. 30, 2002, now U.S. Pat. No. 7,093,150 and claims the benefit under 35 USC 119(e) of prior U.S. Patent Application Ser. No. 60 / 343,165 to Richard Norman, filed on Dec. 31, 2001 and incorporated by reference herein.FIELD OF THE INVENTION[0002]The invention relates to timing on integrated circuits implemented on semiconductor wafers, and more particularly, to the arrangement and management of clock domains in cells of an integrated circuit.BACKGROUND OF THE INVENTION[0003]Electronic signals within large integrated circuits suffer from substantial propagation delays upon being transmitted across the circuit areas. The propagation delays are a function of distance and are due to the parasitic reactances, the small but finite wire resistances and transistor switching times. The problem is further complicated by the fact that these delays are di...

AI Technical Summary

Benefits of technology

[0008]The present invention provides for the arrangement and management of timing various domains on a large integrated circuit which, to mitigate at least one of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies, introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit contemporaneously with data propagating though the circuit. The cells of the integrated circuit are synchronized to this wavefront clock in that the phase offset introduced in a particular cell's clock is such that the arrival of a skewed clock and propagation delayed data from its neighbor is synchronized with that particular cell's own clock. Since the clock propagation delay through each cell itself is being used as the offset for the clock timing of the neighboring cell, the clock frequency is not limited by the clock skew, and since data propagating from cell to cell travels in phase with the wavefront clock, the data does not need to wait for subsequent clock cycles to propagate through the cells.

Problems solved by technology

Electronic signals within large integrated circuits suffer from substantial propagation delays upon being transmitted across the circuit areas.

The propagation delays are a function of distance and are due to the parasitic reactances, the small but finite wire resistances and transistor switching times. The problem is further complicated by the fact that these delays are distributed across the area of the integrated circuit such that their effect on the propagation of the signals is typically not evenly felt everywhere within the area of the circuit.

This problem is commonly referred to as clock skew and leads to errors in the propagation of signals across the circuit.

Various approaches to skew compensation across a single large clock domain can be used, but these approaches typically suffer from inefficiencies in that once a sufficient clock skew has occurred data often must wait for subsequent clock cycles in order to propagate in phase with the clock.

Lowering the clock rate is, however, undesirable because it reduces the processing speed of the integrated circuit.

Half of the problem however remains unsolved.

Although the problem of clock synchronization is solved, the data set will end up out of synchronization with the clock.

In the context of large area circuits, however, this approach does not solve the problems.

Sub-dividing the integrated circuit into cells each having its own clock domain to facilitate high-speed data transfer amongst the cells adjacent to one another can be done with clocks of adjacent cells being synchronized to one another, but this requires integral numbers of clock cycles between cells creating unnecessary delays for short inter-cell connections or for signals that cross many cells.

Hence the rate of data propagation can be limited by the clock frequency.

Another technique is for the cells not to be synced and to have inter-cell signals cross these unsynchronized clock domain boundaries, but this requires substantial amounts of synchronization circuitry to align signals to the clocks of different cells.

All of this additional circuitry for synchronization limits the amount of area on the substrate that can be used for the intended purposes of the integrated circuit.

Images