Method for fabricating electrical interconnect structure

Abstract

A method for fabricating an electrical interconnect structure is adapted for a circuit board manufacturing process. The circuit board comprises a conductive substrate, which comprises a first conductive layer and a bump conductive layer. The bump conductive layer is patterned to form at least one bump over the first conductive layer. Then, a dielectric layer is formed over the first conductive layer and the bump. A second conductive layer is formed over the dielectric layer. At least one blind hole is formed in the second conductive layer and the dielectric layer, passing through the second conductive layer and the dielectric layer to expose the top surface of the bump. A conductive material is filled in the blind hole, and the conductive material in the blind hole and the bump constitute a conductive post.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 93129344, filed Sep. 29, 2004.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a method for fabricating an electrical interconnect structure, and more particularly to a method for fabricating an electrical interconnect structure adapted for a circuit board manufacturing process.[0004]2. Description of the Related Art[0005]A circuit board is composed of a plurality of patterned circuit layers and a plurality of dielectric layers which are alternatively stacked on each other. In addition, methods of forming a circuit board include a laminating process and a build-up process. Either of these methods uses conductive vias to electrically connect these patterned circuit layers. Based on manufacturing process and structure, conductive vias can be divided into conductive through vias and conductive micro vias. According to ...

AI Technical Summary

Benefits of technology

The present invention provides a method for fabricating an electrical interconnect structure for a circuit board manufacturing process that improves the yield of conductive posts. The method involves patterning a conductive layer to form bumps, adding a dielectric layer over the bumps, and forming blind holes in the dielectric layer to expose the bumps. The blind holes are then filled with conductive material to create conductive posts. This method reduces the time for electroplating and decreases the possibility of voids within the conductive posts, resulting in a higher yield of conductive posts.

Problems solved by technology

However, the electroplating layer described above only forms hollow conductive structures, i.e. conductive vias or micro conductive vias, in sidewalls of openings inside the dielectric layer or the stacked layer.

These hollow structures cannot provide desired electrical performance and heat dissipation efficiency required for current circuit boards.

As a result, electrical performance and heat dissipation efficiency of these electrical interconnect structures 100b and 200b will decline.

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