Semiconductor memory device, test circuit and test method

Abstract

Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read / write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read / write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.

Description

FIELD OF THE INVENTION[0001]This invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device, having memory cells in need of refresh for data retention, in which the access speed by refresh may be prevented from being lowered, and to a test method.BACKGROUND OF THE INVENTION[0002]The following analyses are given by the present invention.[0003]Such a semiconductor memory device that comprises a cell array formed by dynamic type memory cells in need of refresh for data retention, and that is adapted to operate as a static random access memory (SRAM), has so far been in use. This type of the semiconductor memory is also termed a pseudo SRAM or a pseudostatic DRAM. There have also been developed a RAM family (termed for example MSRAM) for use of a mobile application, which is functionally compatible with the low power SRAM and which has achieved a high storage capacity by exploiting DRAM memory cells (see Non-Patent Document 1, indi...

AI Technical Summary

Benefits of technology

The present invention relates to a semiconductor memory device and a testing method for testing the device. The invention addresses the problem of interference between read / write operations and refresh operations, which can cause data latency and affect the quality of the device. The invention provides a control circuit that can variably control the latency depending on whether the refresh is before read / write or the read / write is before refresh, and can generate the refresh directly before or after the read / write operation, to reduce the time and cost for testing and improve the quality of the device. The testing method can also set the latency at a fixed value during testing. The technical effects of the invention include reducing the time and cost for testing and improving the quality of the device.

Problems solved by technology

Due to this randomness, overmuch time is taken in testing for checking the interference between the read / write operation and the refresh operation, with the result that the test cost is increased, while the quality of the device can hardly be assured.

However, if the refresh request and the read / write request do not temporally collide one on the other, the probable state of closest proximity of the read / write request to the refresh request cannot be confirmed, as a result of which the quality of the device cannot be assured correctly.

In short, it is not that easy to carry out testing of, for example, the interference between the read / write operation and the refresh, as the read / write operation and the refresh are set to the state of closest proximity to each other.

If an attempt is made to conduct the testing, the result is an increased test cost, as described above.

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