Self-aligned trench contact and local interconnect with replacement gate process

Abstract

A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates generally to semiconductor processes for forming transistors and, more specifically, to processes for forming trench contacts and local interconnects to a replacement gate structure on a semiconductor substrate.[0003]2. Description of the Related Art[0004]Transistors such as planar transistors have been the core of integrated circuits for several decades. During the use of transistors, the size of the individual transistors has steadily decreased through advances in process development and the need to increase feature density. Current scaling employs 32 nm technologies with development also progressing towards 20 nm and beyond technologies (e.g., 15 nm technologies).[0005]Replacement gate processes (flows) are becoming more commonly utilized as they avoid certain problems found in gate first processes. For example, replacement gate processes may avoid problems associated with the stability of the ...

AI Technical Summary

Benefits of technology

This patent describes a new process for making semiconductors more efficiently. By using a special technique, the contacts that connect to the semiconductor can be aligned with the gate, making it simpler and more accurate. This process also reduces the capacitance between the connections, leading to better performance and fewer failures. Overall, this patent provides a better way to make semiconductors more reliably and efficiently.

Problems solved by technology

Additionally, most replacement gate processes suffer from alignment issues when making trench contacts and / or local interconnect connections to the gate.

For example, most replacement gate processes are not self-aligned and can easily fail from misalignment during processing.

It may also be difficult to pattern bidirectional local interconnect and / or reduce the number of interface layers from the local interconnect to either the gate or the source / drain of the gate.

Such process flows, however, are typically very complex, have many resistive interfaces, and have high manufacturing costs due to the complex process flow.

Additionally, there is a low manufacturing margin for misalignments or other errors due to the complexity of the processes as these processes may have severely restrictive design and / or alignment rules.

In addition, there may easily be alignment issues between local interconnect 68C and gate 56′ without restrictive alignment rules.

The numerous process steps may increase the likelihood of resistive interfaces forming between the local interconnects and / or alignment issues between the local interconnects.

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