Three-dimensional non-volatile memory device, memory system including the same and method of manufacturing the same

Abstract

A three-dimensional (3-D) non-volatile memory device includes a plurality of vertical channel layers protruding from a substrate, a plurality of interlayer insulating layers and a plurality of memory cells stacked alternately along the plurality of vertical channel layers, and an air gap formed in the plurality of interlayer insulating layers disposed between the plurality of memory cells, so that capacitance between word lines is reduced to thus improve a program speed.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims priority to Korean patent application number 10-2011-0133739 filed on Dec. 13, 2011, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein.BACKGROUND[0002]1. Field of Invention[0003]The present invention relates generally to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device, a memory system including the same and a method of manufacturing the same.[0004]2. Related Art[0005]A non-volatile memory device retains data even in the absence of a power supply. Two-dimensional memory devices in which memory cells are fabricated in a single layer over a silicon substrate are reaching physical limits, preventing higher levels of integration. Accordingly, three-dimensional non-volatile memory devices in which memory cells are stacked in a vertical direction over a silicon substrat...

AI Technical Summary

Benefits of technology

[0010]An embodiment of the present invention relates to a three-dimensional non-volatile memory device configured to improve the program speed of cells by reducing capacitance between word lines and a method of manufacturing the same.

Problems solved by technology

Two-dimensional memory devices in which memory cells are fabricated in a single layer over a silicon substrate are reaching physical limits, preventing higher levels of integration.

Since the interlayer insulating layer between cells of the conventional 3D structured non-volatile memory device comprises of an oxide layer, there may be excessively high capacitance (A) between the word lines, which may increase the time taken for cells to be programmed.

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