Single chip frame buffer and graphics accelerator

Abstract

A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,694,143. This application is a continuation application of reissue application Ser. No. 09 / 434,331 filed Nov. 5, 1999 issued on Dec. 31, 2002 as RE37,944.<?insert-end id="INS-S-00001" ?>FIELD OF THE INVENTION[0002]This invention relates to computer monitor display controllers for computer terminal displays that use bit-mapped memory, and in particular to a frame buffer memory system and pixel logic connected to the frame buffer memory which processes pixel data prior to application of signals derived therefrom to the computer monitor.BACKGROUND TO THE INVENTION[0003]As is well known, a pixel is a picture element on a computer display which has a certain color. Each logical pixel is actually formed of data defining 3 pixels, a red, green and blue pixel, each of which results in a visually merged, colored point on the display. In this disclosure, the t...

AI Technical Summary

Benefits of technology

[0009]The present invention substantially increases the speed of the graphical and / or video display system of a personal computer or work station, by removing the aforenoted bottleneck. It does so by providing a massively parallel bus between the memory of the display processor and the pixel processor. The data of an entire line of pixels, frame or part of a frame is thereby transferred in parallel between the memory and the pixel processor, whereby the pixel processor processes each bit in parallel with the others that have been transferred. For example, the bus, instead of a maximum 64 bits as in the prior art noted above, can be comprised of 5128 differential bus lines. To provide the massively parallel bus, the architecture of the DRAM memory of the display processor is modified. In addition, to realize the speed gain, both the memory and the display processor, as well as ancillary circuits such as control circuits, decoders, etc., are integrated together into the same integrated circuit.

[0010]With the massively parallel operation of the circuit, circuits are included in embodiments which minimize the impact of sudden and large power requirements from the system power supply, and which minimize power usage in the integrated display processor.

[0017]The novel architecture and novel circuits used therein also provide power saving enhancements, to avoid the massive full power dissipation which would otherwise be required in such a system wherein circuits must operate in parallel on 5128 bits in an IC.

Problems solved by technology

One of the major bottlenecks in a graphics system is the interface throughput between the graphics processor and the frame buffer memory.

Another major bottleneck is between the graphics processor and the RAMDAC.

The power consumed in driving the capacitive loads of these two interfaces represents a significant fraction of overall graphics sub-system power.

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