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Compensation method of a bias magnetic field in a storage surface of a magnetoresistive storage cell, and semiconductor device

A technology for memory cells and semiconductors, applied in the field of compensating this bias field, can solve problems such as reducing the stability of the reference layer

Inactive Publication Date: 2008-05-14
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The biggest effect is that one of the reference sublayers must be used, so destabilizing that reference layer

Method used

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  • Compensation method of a bias magnetic field in a storage surface of a magnetoresistive storage cell, and semiconductor device
  • Compensation method of a bias magnetic field in a storage surface of a magnetoresistive storage cell, and semiconductor device
  • Compensation method of a bias magnetic field in a storage surface of a magnetoresistive storage cell, and semiconductor device

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Embodiment Construction

[0060] Figures 2 and 3 have been described in the introduction.

[0061] FIG. 1 is a simple cross-sectional schematic diagram illustrating a semiconductor device 7 with a magnetoresistive memory cell 6. The cross-sectional schematic diagram is not to scale, and the illustration does not limit the features of the present invention.

[0062] The memory cell 6 is structured by storage, isolation and reference layers 1 , 2 , 3 , and in the illustrated example, the memory cell 6 is mounted on a single layer of the semiconductor device 7 . A passive layer 11 is used parallel to a memory cell layer formed from the memory cells 6 .

[0063] Between the reference of the memory cell 6 and the storage layers 1, 3, ferromagnetic coupling generates a magnetic bias field.

[0064] The components indicated by the dotted lines have the compensation layer 7 provided by the semiconductor device 7, which is omitted in the first embodiment. In the first embodiment, the compensation layer 9 is u...

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PUM

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Abstract

An arrangement is described for compensation of a magnetic bias field in a storage layer of at least one magnetoresistive memory cell provided in a semiconductor device. In this arrangement, at least one compensation layer that is provided with a magnetization compensates for the bias field in the storage layer. A method is also described for compensation of a magnetic bias field in a storage layer of a magnetoresistive memory cell provided in a semiconductor device. A step is provided for applying a ferromagnetic compensation layer. In another step, a bias field is measured in terms of magnitude and direction. In another step, the bias field is compensated by magnetization of the compensation layer.

Description

technical field [0001] The invention relates to a device for compensating a magnetic bias field in a storage layer of a magnetoresistive memory unit used in a semiconductor device. Furthermore, the invention relates to a method of compensating for this bias field. A memory cell based on the magnetoresistance effect is usually stacked with two thin ferromagnetic layers sandwiching a non-ferromagnetic isolation layer with a thickness of several atomic layers. Background technique [0002] One of the two ferromagnetic layers is composed of a hard magnetic material, typically a cobalt-iron alloy. The magnetization has a fixed strength and direction and functions as a reference layer. [0003] A second ferromagnetic layer made of a soft magnetic material, typically nickel-iron alloy, forms a storage layer. Its magnetization is in the same direction or opposite to the magnetization direction of the reference layer, corresponding to the information content of the memory cell. ...

Claims

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Application Information

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IPC IPC(8): G11C11/16G11C11/15H01L21/8246H01L27/105H01L43/08H01L43/12
CPCG11C11/16G11C11/161G11C11/1675G11C11/15
Inventor J·班格特
Owner INFINEON TECH AG
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