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Method for forming CMOS transistor

A technology of transistors and polysilicon layers, which is applied in the direction of transistors, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve the problems of increasing process costs and other issues

Inactive Publication Date: 2008-06-18
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, each process step will increase the process cost, so it is necessary to propose a method that can reduce the process steps

Method used

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  • Method for forming CMOS transistor
  • Method for forming CMOS transistor
  • Method for forming CMOS transistor

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Experimental program
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Embodiment Construction

[0017] The invention provides a method capable of reducing the process steps of low-temperature polysilicon thin film transistors.

[0018] Please refer to FIGS. 2A-2J , which show the manufacturing process of the low temperature polysilicon thin film transistor of the present invention. First, in FIG. 2A, a buffer layer 202 and a polysilicon layer 204 are sequentially formed on a substrate 200, and then a patterned photoresist layer (not shown in the figure) is formed, and photolithography The glue layer is etched for masking to form the polysilicon layer 204 shown in FIG. 2A.

[0019] The substrate 200 of the present invention can be made of glass or plastic, and the polysilicon layer 204 has a thickness of about 200-1000 angstroms, and is formed by crystallizing and tempering an amorphous silicon layer formed on the buffer layer 202 by using an excimer laser. . The two polysilicon layers 204 on the left are used to form a CMOS transistor, and the polysilicon layer 204 on ...

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Abstract

This invention relates to a method for forming a CMOS transistor on a base plate in which, only two implantation steps are needed to form all sources, drains and light doping, firstly form the source and drain of a NMOS transistor utilizing a photoresisive layer covering the source and drain as the shield and implanting a P dopant, then to form a light doping of NMOS and source and drain of PMOS utilizing the said photo resistive layer and the gate as the shield and implanting a B dopant, the dosage of which is smaller than that of the P dopant.

Description

technical field [0001] The present invention relates to a process method for forming CMOS transistors, and in particular to a process method for forming source / drain and lightly doped CMOS transistors by using two implants. Background technique [0002] Most thin film transistors in flat panel displays are made of amorphous silicon (amorphous silicon) process, and a few high-end products are made of polysilicon (poly silicon) process with high electron mobility. Polysilicon technology allows the integration of more electronic circuits, thereby reducing overall product complexity and weight. However, since the maximum temperature in the polysilicon manufacturing process is about 300°C or higher, far exceeding the temperature at which plastics begin to soften, it can only be applied to glass substrates. [0003] Please refer to FIGS. 1A˜1I , which show a manufacturing process of a conventional low temperature polysilicon thin film transistor. First, in FIG. 1A, a buffer laye...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L29/786
Inventor 陈坤宏陈明炎
Owner AU OPTRONICS CORP