Memory data processing method of cache failure processor

A cache invalidation and instruction processing technology, applied in the field of processor access instruction processing where cache access fails, can solve problems such as pipeline blocking, Cache pollution, sacrificing storage bandwidth, etc., to avoid Cache pollution, reduce frequency, The effect of saving memory access bandwidth
CN100399299CActive Publication Date: 2008-07-02LOONGSON TECH CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
LOONGSON TECH CORP
Publication Date
2008-07-02

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Abstract

A method for processing memory-reference command of processor being failed in high speed buffer storage utilizes totally revised Cache block to save memory-reference bandwidth and utilizes predicted-failure poke command to write high speed butter storage or to write lower-layer storage system for sufficiently playing advantages of two treatment methods.
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Description

Technical field

[0001] The present invention relates to the technical field of microprocessor architecture, in particular to a processor memory access instruction processing method with cache memory access failure. Background technique

[0002] With the rapid development of microprocessor design and production technology, the gap between the access speed of the storage system and the computing speed of the processor becomes more and more significant, and the memory access performance has become the bottleneck of the processor. Current processors generally use a cache memory (Cache, hereinafter referred to as "cache") as an effective method for improving the performance of a storage system and an important measure for improving the processing capacity of the processor. The cache is a special memory with small capacity and high speed, which stores the instructions and data recently used by the processor. Limited by the access time, the cache capacity is relatively small. When the p...

Claims

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