Memory data processing method of cache failure processor

Abstract

A method for processing memory-reference command of processor being failed in high speed buffer storage utilizes totally revised Cache block to save memory-reference bandwidth and utilizes predicted-failure poke command to write high speed butter storage or to write lower-layer storage system for sufficiently playing advantages of two treatment methods.

Description

Technical field [0001] The present invention relates to the technical field of microprocessor architecture, in particular to a processor memory access instruction processing method with cache memory access failure. Background technique [0002] With the rapid development of microprocessor design and production technology, the gap between the access speed of the storage system and the computing speed of the processor becomes more and more significant, and the memory access performance has become the bottleneck of the processor. Current processors generally use a cache memory (Cache, hereinafter referred to as "cache") as an effective method for improving the performance of a storage system and an important measure for improving the processing capacity of the processor. The cache is a special memory with small capacity and high speed, which stores the instructions and data recently used by the processor. Limited by the access time, the cache capacity is relatively small. When the p...

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Problems solved by technology

Moreover, not every Cache block will be filled, and the low-level storage system is required to support write-back with a mask bit or write back in multiple write operations, which will sacrifice storage bandwidth.

In short, the disadvantage of the above-mentioned method of writing the cache instruction for cache failure and its improvement method is: if the instruction is used by the subsequent fetch instruction, it can play a role of prefetching; if it is not used by the subsequent The use of the fetch instruction will cause Cache pollution and occupy the Cache port when filling the Cache

The method of writing the low-level storage instruction of the invalid cache instruction will not cause the pollution of the Cache and the additional occupation of the Cache port, but the problem is that the storage instruction does not realize the pre-preparation of the subsequent fetch instruction of the same Cache block. Fetch function; if the invalid store instruction is used by the subsequent fetch instruction of the same Cache block address, the fetch instruction will fail, causing pipeline blockage

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