Bond pad structures and semiconductor devices

Abstract

The invention discloses a welding pad structure and semiconductor device, which comprises the following parts: base, middle structure on the base and welding pad structure on the middle structure, wherein the middle structure contains first metal layer to support welding pad structure, multiple second metal layers under the welding pad structure as power wire. The invention doesn't damage circuit element on the bottom of circuit area, which can reduces size of semiconductor chip.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to a semiconductor device having a bond pad structure formed in a circuit area. Background technique [0002] In general, the performance of semiconductor devices can be improved by increasing device density and device packaging density due to reduction in device size. The increase in device density has resulted in a demand for the number of interconnect structures in the semiconductor device, which is closely related to the packaging requirements of the semiconductor device. One of the main considerations in package design is when one or more devices are installed in the package, the I / O capability or access capability of the semiconductor device or the package. [0003] In a general semiconductor device package, the semiconductor chip is installed or disposed in the package, and the package is further connected to the inside of a substrate by conductive connections such as...

AI Technical Summary

Problems solved by technology

However, since the bonding pads 16 occupy most of the surface of the semiconductor chip 10, the above layout design cannot effectively reduce the size of the overall chip, which is not conducive to the reduction of manufacturing costs.

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