Method for reading out stored data in system storage by display controller

Abstract

A method for display controller to read data from the system memory includes such steps as setting up a block capacity limit value by the memory controller, dividing the memory read instruction sequence into several instruction segments according to the said block capacity limit value in such a manner that the total data amount read by a segment can not be greater than the block capacity limit value, and regulating the order of read instructions of several instructions in a segment need to read the data from the same page of memory for decreasing the switchings between pages.

Description

technical field [0001] The invention provides a method for reading data in a memory device, and particularly relates to a method for a display controller to read data in a system memory. Background technique [0002] With the development of multimedia technology, image output has gradually become an important task of computer devices. That is to say, a graphics card must not only perform simple 2D image processing, but also must be able to perform complex 3D image data calculations. Referring to FIG. 1 , FIG. 1 is a functional block diagram of a known computer device 10 . The computer device 10 includes a central processing unit 12 , a north bridge circuit 14 , a south bridge circuit 16 , a graphics chip 18 , a graphics memory 20 , a display device 22 , a system memory 24 and an input device 26 . The central processing unit 12 is used to control the overall operation of the computer device 10, the north bridge circuit 14 is used to coordinate the signal transmission between...

AI Technical Summary

Problems solved by technology

[0005] As mentioned above, although the graphics chip 18 can continuously output a plurality of read instructions to the storage controller 15 in a pipelined manner so as to read the system memory 24, during the data read operation, when two read instructions respectively read When fetching data on different pages, the system memory 24 must perform the operation of closing the page (such as PreA) and the operation of activating the page (such as ActA, ActB), so the above-mentioned operations of closing the page and opening the page will cause the system memory 24 to be in A delay time (period L as shown in FIG. 3 ) is generated in the data reading process. In other words, when the multiple read instructions are used to respectively read the stored data on multiple pages, the storage controller 15 must control The system memory 24 is constantly switched between each page, so when the bus of the known graphics acceleration port interface is transmitting data to the graphics chip 18, the bus will wait to receive the system memory 24 because of the delay time of the system memory 24 output data, thus making the data transfer inefficient for the bus known as the accelerated graphics port interface

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