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Integrated circuit chip and package

A technology of integrated circuits and chips, which is applied in the direction of circuits, electrical components, electrical solid devices, etc., and can solve problems such as severe electrical interference

Inactive Publication Date: 2009-07-22
INTEGRANT TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Especially, when two IC chips 122 and 123 process different signals, electrical interference becomes serious

Method used

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  • Integrated circuit chip and package
  • Integrated circuit chip and package
  • Integrated circuit chip and package

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] Hereinafter, implementation of the present invention will be described in detail with reference to the accompanying drawings.

[0039] In general, electrical connection between a substrate and an IC chip is classified into a wire connection method and a flip chip connection method according to package types. According to the wire bonding method, a substrate on which leads are formed is electrically connected to a semiconductor chip using miniaturized wires. According to the flip chip connection method, a substrate and a semiconductor chip are connected to each other through protrusion units, such as junctions of bumps or solder balls of the semiconductor and the substrate. In particular, when a semiconductor chip and a substrate are bonded together, the flip-chip connection method gives more space than the wire method, thus allowing package miniaturization. The flip chip connection method is one of the surface configuration technologies. More particularly, when an ele...

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Abstract

An integrated circuit chip and package supported by a device or semiconductor chip are provided. The integrated circuit chip includes a substrate, a device portion, and a first integrated circuit chip. A device portion is formed on the substrate, and a first integrated circuit chip is formed on the device portion. The area occupied by the integrated circuit chip is reduced. This reduction in area allows for miniaturization of devices, reduction in cost, and improvement in productivity, as well as minimization of the occurrence of electrical interference between integrated circuit chips. Therefore, performance degradation can be prevented.

Description

[0001] This nonprovisional application claims the benefit of Patent Application No. 10-2006-0014268, filed in the Republic of Korea on February 14, 2006, under 35 U.S.C § 119(a), the entire contents of which are hereby incorporated by reference refer to. technical field [0002] This application relates to integrated circuit (IC) chips and packages. [0003] In the manufacturing process of semiconductor chips, after completion of many processes including etching and deposition applied on a wafer substrate, the resulting devices are tested and packaged together. Typical packaging involves the process of disposing a semiconductor chip on a substrate on which leads are formed and molding the disposed semiconductor chip with a synthetic molding material such as plastic. Background technique [0004] Conventional packaging of more than two IC chips in relation to each other is described in detail below. [0005] Figure 1a Two packaged IC chips are shown. The two IC chips 101 ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L25/16H01L23/488
CPCH01L2924/01015H01L2924/19105H01L2924/01082H01L2924/01004H01L2924/09701H01L2225/06575H01L2225/06555H01L2924/01027H01L2924/19041H01L2224/48091H01L25/16H01L2224/49171H01L25/0652H01L23/66H01L2924/014H01L24/49H01L2924/19043H01L2224/48145H01L25/18H01L2924/14H01L2924/01005H01L2924/01033H01L2924/19042H01L2924/01006H01L2225/0651H01L2924/3025H01L2924/19103H01L2225/06506H01L24/48H01L2224/05554H01L2924/00014H01L2924/181H01L2924/00H01L2224/45099H01L2224/05599H01L2924/00012H01L27/00
Inventor 千硕杓金炅吾金宝垠
Owner INTEGRANT TECH