Layout structure of non-volatile memory

Abstract

A layout structure of a non-volatile memory, which includes: a substrate, a plurality of embedded bit lines in a row direction, a plurality of transistors as memory cells, a plurality of word lines in a column direction, a plurality of bit line contact windows and at least Two virtual character lines. There is an isolation structure in the substrate, and the isolation structure defines an active area. The buried bit line is located in the base of the active area. Transistors are located on the substrate between the buried bit lines and arranged in a two-dimensional array. Each word line connects the transistors of the same column in series. The bitline contacts are located on the buried bitlines. In addition, the two dummy word lines are respectively located on the isolation structures on both sides of the active area, and are arranged parallel to the word lines.

Description

technical field [0001] The present invention relates to a layout structure of a semiconductor device, and more particularly, to a layout structure of a non-volatile memory. Background technique [0002] With the rapid development of science and technology, when the functions of computer microprocessors are getting stronger and stronger, and the programs and operations performed by software are getting larger and larger, the demand for memory is also getting higher and higher, especially regarding the layout of memory components. The requirement for the accuracy of layout rules, and in order to manufacture to meet this demand trend, improving the technology of making memory devices has become the driving force behind the continuous challenge of high integration in semiconductor technology. [0003] Generally speaking, in the manufacturing process of the entire memory array, there are many variation factors, which will adversely affect the yield and reliability of the process....

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Problems solved by technology

[0003] Generally speaking, in the manufacturing process of the entire memory array, there are many variable factors, which will have a negative impact on the yield and reliability of the process.

For example, due to the limitation of the photolithography process, the critical dimension (Critical Dimension, CD) deviation (bias) between the components in the edge area of ​​the memory array and the components in the central area will occur, which will directly or indirectly cause defects (such as leakage current, short circuit, etc.) etc.), affecting the yield and reliability of the process

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