Electro-static discharge protecting device and method for fabricating the same

Abstract

Provided are an ESD protection device and a manufacturing method thereof. The ESD protection device includes first and second device isolation layers, first and second high-concentration second-conductivity-type impurity regions, high-concentration first-conductivity-type impurity regions, and low-concentration first-conductivity-type impurity regions. The first and second device isolation layers are formed in field regions on a semiconductor substrate of a first conductivity type. First and second high-concentration second conductivity type impurity regions are formed on the first conductivity type semiconductor substrate. A high concentration first conductivity type impurity region is formed on a portion of the first semiconductor substrate on one side of the second high concentration second conductivity type impurity region. The low-concentration first conductivity type impurity region is formed in a portion of the semiconductor substrate below the first high-concentration second conductivity type impurity region.

Description

technical field [0001] The present invention relates to electrostatic discharge (ESD) protection devices and methods of making the same. Background technique [0002] Typically, ESD occurs when a user, charged with static electricity due to friction and induction, touches an electronic component. Likewise, integrated circuits (ICs), particularly ICs that include metal oxide semiconductor (MOS) transistors, are susceptible to damage from ESD. ESD charges can be transferred to input / output pads, power supply pins, or other IC pads, causing fatal damage to semiconductor junctions, dielectrics, interconnect components, or components of the IC. [0003] For state-of-the-art semiconductor devices that are reduced in size and increased in integration, ESD protection devices are used to protect ESD-sensitive components. Here, the ESD protection device uses a gate-grounded NMOS (GGNMOS), which uses a lateral parasitic bipolar characteristic of a MOS transistor. [0004] That is, p...

AI Technical Summary

Problems solved by technology

[0011] However, prior art field transistors have a high breakdown voltage, which makes it difficult to protect internal components from ESD

Therefore, prior art field transistors are not suitable for ESD protection devices

Images