Multi-position quasi memory cell operation method

Abstract

A method for operating a multi-level memory unit, wherein the multi-level memory unit includes a substrate of a first conductivity type, a control gate, a charge storage layer and two source / drain regions of a second conductivity type. The operation method includes an erasing step of injecting first-type charges into the charge storage layer, and a programming step. The programming step includes applying a first voltage to the substrate, a second voltage to the source / drain regions, and a third voltage to the control gate. Wherein, the difference between the first and second voltages is sufficient to generate band-tunneling hot holes in the substrate, and the third voltage can inject the second type charges into the charge storage layer. There are 2n-1 types of the third voltage, wherein n≥2, so as to program the multi-level memory cell to a predetermined storage state among the 2n-1 storage states.

Description

technical field [0001] The present invention relates to a method of operating a semiconductor device, and in particular to a method of operating a multi-level memory cell (Multi-Level Cell, MLC) for a non-volatile memory, which utilizes a double-sided bias (Double -Side Bias, DSB)-Band-To-Band Tunneling Hot Hole (BTBTHH) effect for programming. Background technique [0002] With the rapid growth of information flow, the demand for storage capacity of commonly used electrically erasable programmable non-volatile memory (programmable non-volatile memory) such as flash memory (flash memory) in the market is also increasing. [0003] In order to increase the storage capacity per unit area of ​​non-volatile memory products, the most direct method is to reduce the area of ​​each storage unit, but this method is limited by factors such as the resolution of the lithography process and the electrical properties of the components related to the size. Another method is to make each me...

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Problems solved by technology

[0005] However, due to the poor efficiency of injecting or ejecting electrons by using the FN tunneling effect, the erasing action and programming action in the known multi-level memory cell operation method are relatively slow

In addition, since the above-mentioned operation method is to expel electrons from the charge storage layer for erasing, the initial voltage of each memory cell in the erasing state is relatively low, resulting in more leakage

Furthermore, since the above-mentioned programming operation of controlling the starting voltage by the length of the programming time is not easy to precisely control the quantity of injected electrons, the starting voltage distribution range of each storage state memory cell is very wide, and it is easy to read. misjudgment

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