Multi-position quasi memory cell operation method

Abstract

The invention relates to a method for operating a multi-bit quasi memory cell; the multi-bit quasi memory cell comprises a first conductive basement, a control gate, a charge storage layer and two second conductive source cathode / drain areas. The operation includes an erasing step in which a first form charge is injected into the charge storage layer and a programmed step. The programmed step includes the processes: a first voltage is applied on the basement; a second voltage is applied on the two source cathode / drain areas and a third voltage is applied on the control gate. The difference value of the first voltage and the second voltage is sufficient to generate a channel-passing thermoelectric tunnel of a frequency band and the third voltage can allow a second form charge to be injected into the charge storage layer. The third voltage has 2-1(n is more than or equal to 2) sorts so that the multi-bit quasi memory cell is programmed to a predetermined storage state in 2-1 storage states.

Description

technical field [0001] The present invention relates to a method of operating a semiconductor device, and in particular to a method of operating a multi-level memory cell (Multi-Level Cell, MLC) for a non-volatile memory, which utilizes a double-sided bias (Double -Side Bias, DSB)-Band-To-Band Tunneling Hot Hole (BTBTHH) effect for programming. Background technique [0002] With the rapid growth of information flow, the demand for storage capacity of commonly used electrically erasable programmable non-volatile memory (programmable non-volatile memory) such as flash memory (flash memory) in the market is also increasing. [0003] In order to increase the storage capacity per unit area of ​​non-volatile memory products, the most direct method is to reduce the area of ​​each storage unit, but this method is limited by factors such as the resolution of the lithography process and the electrical properties of the components related to the size. Another method is to make each me...

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Problems solved by technology

[0005] However, due to the poor efficiency of injecting or ejecting electrons by using the FN tunneling effect, the erasing action and programming action in the known multi-level memory cell operation method are relatively slow

In addition, since the above-mentioned operation method is to expel electrons from the charge storage layer for erasing, the initial voltage of each memory cell in the erasing state is relatively low, resulting in more leakage

Furthermore, since the above-mentioned programming operation of controlling the starting voltage by the length of the programming time is not easy to precisely control the quantity of injected electrons, the starting voltage distribution range of each storage state memory cell is very wide, and it is easy to read. misjudgment

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