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Memory controller and memory control method

A storage controller and storage technology, applied in storage systems, instruments, static indicators, etc., can solve the problem that the first storage and the second storage are difficult to guarantee the data transmission band, so as to improve the use efficiency and ensure the data transmission band pass. Effect

Inactive Publication Date: 2010-02-03
SONY CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, if such a transfer is used, it is difficult to ensure a stable data transfer rate between the first memory and the second memory.

Method used

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Embodiment Construction

[0130] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. figure 1 The configuration of one embodiment of the image signal processing apparatus 100 according to the present invention is shown. The image signal processing device 100 converts an input image signal Sa into an output image signal Sb. Although the following description is made on the assumption that the image signal Sa is a 480i signal and the image signal Sb is a 1080i signal for the convenience of explanation, the present invention is not limited to this example. The 480i signal is an interlaced image signal, in which the number of scanning lines is 525, the number of effective scanning lines is 480, the effective pixel number is horizontal × vertical = 720 × 480, and the sampling frequency is 13.5 MHz (see Figure 2A ). The 1080i signal is an interlaced image signal, in which the number of scanning lines is 1125, the number of effective scanning lines is ...

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Abstract

A luminance signal Ya and a color-difference signal Ua / Va constituting an input image signal is transferred to a frame memory (first memory) in the unit of line synchronously with its horizontal synchronous signal and written therein. A memory TG211 reads out a read-out request RRQ. The cycle of this request RRQ is a time computed based on a single vertical effective period of an output image signal Sc and the number of lines objective for rate conversion of an input image signal Sa. The luminance signal Ya and color-difference signal Ua / Va are transferred in the unit of line from the frame memory to rate conversion units (second memory) through buffers. There occurs no deflection in this transfer cycle and in each transfer cycle, the stable data transmission band can be secured.

Description

[0001] This application is a divisional application of a patent application whose application date is August 19, 2004, and the application number is 200410082227.1, titled "Memory Controller and Method, Ratio Conversion Device and Method, Image Signal Processing Device and Method". Technical field [0002] The present invention relates to a storage controller, a storage control method, a ratio conversion device, a ratio conversion method, an image signal processing device, an image signal processing method, and a program for executing each of the above-mentioned methods. [0003] More specifically, the present invention relates to a memory controller and the like which are more suitable when converting the number of pixels to another for a display. Background technique [0004] Well-known displays include flat panel displays, liquid crystal displays (LCD), plasma displays (PDP), and the like. The definition of the image quality of these three displays depends on the number of pixels...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/20G06F12/00G09G5/00H04N7/01
Inventor 根本光太郎近藤哲二郎朝仓伸幸井上贤新妻涉石井达也绫田隆秀山中政宣立平靖
Owner SONY CORP