Data reading method of wishbone system structure

Abstract

Characters of the invention are that the method includes following steps: master unit send 'read' command to slave unit, and the flag bit TAGN_O of the 'read' command is in use for indicating length of data needed to read; TAGN_O of master unit is connected to TAGN_I of slave unit; slave unit reads back data in the said length from data interface; returns the data reads back to master unit. Comparing prior art, the disclosed method makes Wishbone slave unit know how many data needed to read for master unit when receiving 'read' command. Thus, slave unit can adjust own action to access anther interface based on data needed to read for master unit so as to prevent wasting bandwidth, and increasing time delay.

Description

technical field [0001] The invention relates to a Wishbone architecture used for system interconnection on a chip, in particular to a method for reading data in the Wishbone architecture. Background technique [0002] Wishbone is an architecture for system-on-chip (SOC) system interconnection introduced by Silicore. It is widely used in on-chip interconnection systems because of its simple hardware structure, high interconnect throughput, and open and free features. [0003] Four modules are defined in the Wishbone architecture: master device, slave device, connection module and system module. Among them, the system module generates the clock and reset signal of the entire Wishbone system, the connection module is responsible for connecting the master device and the slave device, and the main data exchange occurs between the master device and the slave device module. The Wishbone master device is the initiator of operations on the Wishbone interface, which can actively issu...

AI Technical Summary

Problems solved by technology

Under normal circumstances, the slave device does not know how much data the master device needs, and the slave device does not know whether the master device needs new data until all the read data it obtains from the PCI interface returns, so the following two wastes are likely to occur Efficiency situation: 1) The data read back from the PCI interface by the slave device is less than that required by the master device. At this time, the slave device must initiate a read operation on the PCI interface again, and then return the data to the master device after the PCI interface returns the data , a read operation of the master device becomes multiple read operations fully serialized on another PCI interface, the PCI may be idle, the bandwidth is not fully utilized, and the delay in returning data from the slave device to the master device is also the worst; 2) The data read back from the device is more than the master device needs, so the bandwidth on the PCI interface of the slave device is wasted. If the other interface is a shared bus structure, this waste will affect the performance of all devices on the shared bus

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