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X87 fused multiplication-addition instruction and its use

An instruction and fusion technology, used in instruction analysis, program control design, instrumentation, etc., to solve the problem of not including floating-point fusion multiply-add instructions.

Active Publication Date: 2008-03-19
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the instruction set of the most mainstream X86 architecture microprocessor currently does not contain floating-point fused multiply-add instructions

Method used

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  • X87 fused multiplication-addition instruction and its use
  • X87 fused multiplication-addition instruction and its use
  • X87 fused multiplication-addition instruction and its use

Examples

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Embodiment Construction

[0019] Referring to FIG. 1 , the structural block diagram shows a microprocessor 100 of X86 architecture whose instruction set includes X87 Fused Multiply-Add (FMA) instruction. The microprocessor 100 includes an instruction register 102, which caches program instructions fetched from a system memory coupled to the microprocessor 100. According to the present invention, the program instructions include X87 fused multiply-add instructions. The microprocessor 100 further includes an instruction fetcher 104 coupled to the instruction register 102 for fetching program instructions from the instruction register 102 and the system memory. The microprocessor 100 also includes an instruction decoder 106, coupled to the instruction fetcher 104, which decodes the obtained program code of the instruction set of the microprocessor 100, such as the X87 fusion multiply-add instruction described in the present invention. . The instruction scheduler 108 is coupled to the instruction decoder ...

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Abstract

An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.

Description

technical field [0001] The present invention relates to a floating-point instruction executed in a pipeline microprocessor, more specifically, a fusion multiply-add instruction executed in an X87 instruction set architecture. Background technique [0002] The instruction sets of some microprocessors, microcontrollers, and digital signal processors include a Fused Multiply-Add (FMA) instruction. A floating-point fused multiply-add instruction multiplies two floating-point operands (A and B) and adds their product to a third floating-point operand (C), namely: [0003] FMA(A,B,C)=(A*B)+C [0004] A microprocessor that includes a fused multiply-add instruction in its instruction set improves the speed and accuracy of many important operations involving multiply-accumulate, compared to a microprocessor that requires the program to execute a single multiply instruction followed by a single add instruction , such as matrix multiplication, dot product operations, or polynomial ex...

Claims

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Application Information

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IPC IPC(8): G06F9/302
CPCG06F9/3001G06F7/483G06F7/5443G06F9/30014G06F9/30163G06F9/30145G06F7/78
Inventor G·格伦·亨利特里·帕克斯蒂莫西·A·埃利奥特
Owner VIA TECH INC
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