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Repositioning system and method

A reset terminal and reset request technology, applied in the reset field, can solve problems such as failure analysis, loss of recorded data, and low system stability, and achieve the effects of facilitating failure causes, improving stability, and facilitating analysis

Active Publication Date: 2010-07-07
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The inventor found that the sudden reset of the processor will produce many adverse effects, such as failure to restart, loss of recorded data, failure to save some data before the failure for failure analysis, etc.
figure 2 It shows an example where the processor is suddenly reset and cannot be restarted: because the processor is suddenly reset when the processor reads the SDRAM memory, the bus is controlled by the memory, and when the processor is restarted, it cannot be started by reading the bus. The launcher in the module
[0011] Therefore, in the prior art, because the processor cannot predict the reset, emergency measures cannot be taken before the reset, such as saving data, shielding interrupts, stopping certain operations, etc., resulting in low system stability, and it is difficult to analyze the cause of the reset fault

Method used

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  • Repositioning system and method
  • Repositioning system and method
  • Repositioning system and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] A schematic structural diagram of a processor predictive reset system is shown in FIG. 3 a , including: a processor 301 and a delay module 302 .

[0035] When a reset source of the processor 301 needs to reset the processor 301 for some reason, and reset the reset source through the reset of the processor, for example, an external device failure needs to be reset, or a watchdog overflow needs to be reset and cleared , then these reset sources will output a valid signal - reset request signal.

[0036] The reset request signal is sent to the interrupt terminal of the processor 301, and the processor 301 knows that there is a reset demand by receiving the input signal of the interrupt terminal, so as to predict the reset and take pre-reset measures, such as recording the interrupt source, saving data, stopping certain operations, etc. .

[0037]The reset request signal is also sent to the delay module 302 at the same time. The delay module 302 is used to delay the reset ...

Embodiment 2

[0056] A schematic structural diagram of a processor predictive reset system is shown in FIG. 4 a , including: a processor 401 , a watchdog module 402 , and a delay module 404 .

[0057] When the program of the processor 401 is running normally, the processor 401 sends a reset signal from the IO port to the reset terminal of the watchdog module 402 at regular intervals. After the watchdog module 402 receives the reset signal, it will reset the timer.

[0058] When the program of the processor 401 cannot run normally due to interference, or failure of external equipment, etc., the program of the processor 401 "runs away", causing the processor 401 to fail from the IO port to the watchdog module 402 at regular intervals. The clear terminal sends a clear signal. Since the timer of the watchdog module 402 is not cleared, it will keep timing until it overflows, and outputs an overflow signal. The watchdog module 402 is used to monitor the operating condition of the processor, whi...

Embodiment 3

[0084] A structural diagram of a processor reset system according to an embodiment of the present invention, as shown in FIG. 5 a , includes: a processor 501 , a watchdog module 502 , a logic gate module 503 , and a delay module 504 .

[0085] When the program of the processor 501 is running normally, the processor 501 will send a reset signal from the IO port to the reset terminal of the watchdog module 502 at regular intervals. After the watchdog module 502 receives the clear signal, it will clear the timer.

[0086]When the program of the processor 501 cannot run normally due to interference or failure of external equipment, etc., the program of the processor 501 "runs away", causing the processor 501 to fail to transfer from the IO port to the watchdog module 502 at regular intervals. The clear terminal sends a clear signal. Since the timer of the watchdog module 502 is not cleared, it will keep timing until it overflows. The watchdog module 502 can be embedded in the pr...

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Abstract

This invention relates the reset technology especially a kind of foreknowledge reset technology using the processor. A kind of processor reset system concludes: processor and watchdog module and the watchdog module is used to monitor the running state of processor and when the processor is abnormal it outputs the reset request signal; the processor readies to reset according to the received resetrequest signal by the processor and outputs the time-delay reset triggering signal; the watchdog module makes the timer of watchdog module zero cleared and reset according to the received reset triggering signal and outputs the reset signal to the processor and then the processor does reset after receiving the reset signal. Before the processor is reset we can adopt the emergency measures in order to ensure the system to start again successfully thus enhance the system's stability and easy to analyze the failure cause.

Description

technical field [0001] The invention relates to a reset technology, in particular to a technology for enabling a processor to predict reset. Background technique [0002] In many control occasions, a processor is generally used to control, respond or signal process the entire circuit. This kind of processor is generally CPU, DSP, one-chip computer, FPGA etc. [0003] When the field circuit is working, it will encounter various accidents, such as electromagnetic interference, no response of external equipment, abnormal communication interruption, etc. At this time, the normally running program in the processor will appear to "run away", that is, the program cannot perform work in a normal order, control the entire circuit, and the entire circuit will be in a state of control chaos. [0004] For the automatic control and operation system, if this chaotic state cannot be discovered and dealt with in time, it will cause unpredictable consequences, causing normal control and co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/24G06F11/00
Inventor 徐海东
Owner HUAWEI TECH CO LTD