Repositioning system and method
A reset terminal and reset request technology, applied in the reset field, can solve problems such as failure analysis, loss of recorded data, and low system stability, and achieve the effects of facilitating failure causes, improving stability, and facilitating analysis
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Embodiment 1
[0034] A schematic structural diagram of a processor predictive reset system is shown in FIG. 3 a , including: a processor 301 and a delay module 302 .
[0035] When a reset source of the processor 301 needs to reset the processor 301 for some reason, and reset the reset source through the reset of the processor, for example, an external device failure needs to be reset, or a watchdog overflow needs to be reset and cleared , then these reset sources will output a valid signal - reset request signal.
[0036] The reset request signal is sent to the interrupt terminal of the processor 301, and the processor 301 knows that there is a reset demand by receiving the input signal of the interrupt terminal, so as to predict the reset and take pre-reset measures, such as recording the interrupt source, saving data, stopping certain operations, etc. .
[0037]The reset request signal is also sent to the delay module 302 at the same time. The delay module 302 is used to delay the reset ...
Embodiment 2
[0056] A schematic structural diagram of a processor predictive reset system is shown in FIG. 4 a , including: a processor 401 , a watchdog module 402 , and a delay module 404 .
[0057] When the program of the processor 401 is running normally, the processor 401 sends a reset signal from the IO port to the reset terminal of the watchdog module 402 at regular intervals. After the watchdog module 402 receives the reset signal, it will reset the timer.
[0058] When the program of the processor 401 cannot run normally due to interference, or failure of external equipment, etc., the program of the processor 401 "runs away", causing the processor 401 to fail from the IO port to the watchdog module 402 at regular intervals. The clear terminal sends a clear signal. Since the timer of the watchdog module 402 is not cleared, it will keep timing until it overflows, and outputs an overflow signal. The watchdog module 402 is used to monitor the operating condition of the processor, whi...
Embodiment 3
[0084] A structural diagram of a processor reset system according to an embodiment of the present invention, as shown in FIG. 5 a , includes: a processor 501 , a watchdog module 502 , a logic gate module 503 , and a delay module 504 .
[0085] When the program of the processor 501 is running normally, the processor 501 will send a reset signal from the IO port to the reset terminal of the watchdog module 502 at regular intervals. After the watchdog module 502 receives the clear signal, it will clear the timer.
[0086]When the program of the processor 501 cannot run normally due to interference or failure of external equipment, etc., the program of the processor 501 "runs away", causing the processor 501 to fail to transfer from the IO port to the watchdog module 502 at regular intervals. The clear terminal sends a clear signal. Since the timer of the watchdog module 502 is not cleared, it will keep timing until it overflows. The watchdog module 502 can be embedded in the pr...
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