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Erasing non-volatile memory utilizing changing word line conditions to compensate for slower frasing memory cells

A non-volatile storage and volatile memory technology, applied in the semiconductor field, can solve the problems of increasing programming and erasing time, short cycle life of memory strings, etc.

Active Publication Date: 2010-09-01
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, software programming can increase program and erase times
Also, different erase rates can lead to shorter cycle life of memory strings

Method used

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  • Erasing non-volatile memory utilizing changing word line conditions to compensate for slower frasing memory cells
  • Erasing non-volatile memory utilizing changing word line conditions to compensate for slower frasing memory cells
  • Erasing non-volatile memory utilizing changing word line conditions to compensate for slower frasing memory cells

Examples

Experimental program
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Effect test

Embodiment Construction

[0054] Figure 4 It is a block diagram of an embodiment of a flash memory system that can be used to implement the present invention. Other systems and implementations can be used. The memory cell array 302 is controlled by a column control circuit 304, a row control circuit 306, a c source control circuit 310, and a p-well control circuit 308. The column control circuit 304 is connected to the bit line of the memory cell array 302 for reading the data stored in the memory cell, for determining the state of the memory cell during a programming operation, and for controlling the potential of the bit line Level to facilitate or prohibit programming and erasing. The row control circuit 306 is connected to the word line to select one of the word lines, applies a read voltage, applies a program voltage combined with the bit line potential level controlled by the column control circuit 304, and applies an erase voltage. C source control circuit 310 controls the common source line c...

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Abstract

The voltage conditions stressed to a memory unit in a nonvolatile memory system during the erasing period are changed so that a selecting memory unit is balance to the erasing operation of other memory units which are erased right now in the system. The changed conditions can compensate the capacitance coupling voltage inside a NAND string. When erasing operation is carried on the offset NAND string and erasing voltage pulse is stressed on the offset NAND string, the word line of one or more inner memory unit can be floated, thereby forming a peak erasing potential which is lower than the normal potential on a unit channel electric medium coupled to the word line. Therefore, the erasing speed of the units is reduced so as to be matched with the tail memory units which have a relatively slow erasing speed. The erasing operation of different memory units can be changed with different amount by floating different word line in different time.

Description

[0001] claim priority [0002] This application claims priority to U.S. Provisional Patent Application No. 60 / 667,043, filed March 31, 2005, by Hemink et al., entitled "NON-VOLATILEMEMORY ERASE OPERATIONS WITH OVER-ERASE PROTECTION," which Incorporated herein by reference in its entirety. [0003] Cross References to Related Applications [0004] The following applications are cross-referenced herein and incorporated by reference in their entirety: [0005] U.S. Patent Application No. 11 / 296,032, filed December 6, 2005, by Masaaki Higashitani, entitled "SYSTEMS FORERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD LINECONDITIONS TO COMPENSATE FOR SLOWER ERASING MEMORY CELLS" (Docket No. SAND-01054US2) ; [0006] U.S. Patent Application No. 11 / 025,620 (Docket No. SAND-01023US0), filed December 29, 2004, by Wan et al., entitled "WORD LINE COMPENSATIONIN NONVOLATILE MEMORY ERASE OPERATIONS"; [0007] U.S. Patent Application No. 11 / 296,055 (Docket No. SAND-01066US0), entitle...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/04G11C16/16
CPCG11C16/3409G11C16/08G11C2216/18G11C16/345G11C16/12G11C16/0483G11C16/3404G11C11/5635G11C16/3477G11C16/16G11C2211/5621G11C16/3454G11C16/3468G11C11/5628G11C8/08G11C16/3445G11C16/3472G11C16/14
Inventor 东谷正昭
Owner SANDISK TECH LLC