4-level logic decoder

Abstract

The present invention relates to a 4-level logic decoder for decoding n 4-level input data signals into n 2-bit signals. The 4-level logic decoder comprises n decoding circuits (120) with each decoding circuit comprising comparison circuitries (125) for comparing the 4-level input data signal with a clock signal and a one-bit data signal. In dependence upon the comparison results signals are provided to a decode logic circuit (138), which are indicative of a data bit value of the 4-level input data signal representing one of the clock signal, the one-bit data signal, and static values of the 4-level input data signal. In dependence upon the signals the decode logic circuit (138) generates then a 2-bit output data signal. The 4-level logic decoder is easily implemented using simple circuit of logic components, which allow modeling using an HDL.

Description

[0001] This application claims application S / N: 60 / 702,052 (Attorney Docket No. 002087US1) entitled "An Efficient Implementation of a 4-Level. N-Wire to 2N-Bit Logic Decoder," filed July 22, 2005 priority, and this document is incorporated herein by reference in its entirety. technical field [0002] The present invention relates generally to multilevel logic, and more particularly to a circuit for decoding n 2-bit data from a 4-level logic data path used in conjunction with a high-speed serial bus. Background technique [0003] High-speed serial buses are used in a variety of applications, including computer systems, computer networks, and telecommunications systems. The goal is to transfer as much data as possible, as quickly as possible, and as accurately as possible. Traditional digital circuits use only two levels, high or low - corresponding to the binary value '1' or '0' in a data bit. An alternative to traditional digital circuits is to use multi-level encoded data...

AI Technical Summary

Problems solved by technology

Current 4-level logic decoders use delay cells to detect differences between dynamic and static signals, and use flip-flops to store these differences and iterate over the 2-bit data sequentially, so this complicates the design

In addition, the use of delay cells prevents the use of hardware design language (HDL) to model the decoding circuit, which requires manual gate level implementation and manual timing verification

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