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A built-in controllable silicon for reverse phase part

A technology of inverters and polysilicon layers, which is applied in the direction of electric solid-state devices, semiconductor devices, semiconductor/solid-state device components, etc., and can solve problems such as difficult adjustment, high SCR trigger voltage, and increased cost.

Inactive Publication Date: 2008-08-06
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the SCR trigger voltage is generally high, and it is not easy to adjust, which greatly limits its application range
For this, as shown in Figure 3, an effective solution is to build an auxiliary trigger circuit by adding capacitors, resistors, and inverters, but this solution increases the area of ​​an additional inverter and increases the cost

Method used

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  • A built-in controllable silicon for reverse phase part
  • A built-in controllable silicon for reverse phase part
  • A built-in controllable silicon for reverse phase part

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Embodiment Construction

[0019] As shown in FIG. 4 and FIG. 5 , a thyristor embedded in an inverter includes a P-type substrate 40 on which an N well 41 and a P well 49 are closely connected.

[0020] From N well 41 to the direction of P well 49, described N well (41) and P well (49) are successively provided with first N+ implantation region 42a, first P+ implantation region 44a, second P+ implantation region 44b, The second N+ implantation region 42b, the third N+ implantation region 42c and the third P+ implantation region 44c, the boundary of the P well 49 and the N well 41 is located below the second P+ implantation region 44b.

[0021] Between the first N+ implantation region 42a and the first P+ implantation region 44b, the third N+ implantation region 42c and the third P+ implantation region 44c are separated by a shallow moat 43, and the second P+ implantation region 44b and the second N+ implantation region 42b are closely connected .

[0022] The surface of the N well 41 between the first ...

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Abstract

The invention discloses a silicon control embedded in an inverter which comprises a P type substrate provided with an N well and a P well closely connected, the N well points to the P well, a first N+ injection section, a first P+ injection section, a second P+ injection section, a second N+ injection section, a third N+ injection section and a third P + injection section are orderly arranged on the N well and the P well; the boundaries of the P well and the N well are positioned under the second P+ injection section, shallow trenches separate the first N+ injection section and the first P+ injection section, the third N+ injection section and the third P+ injection section; the second P+ injection section is closely connected with the second N+ injection section; one poly-silicon layer covers the surface of the N well between the first P+ injection section and the second P+ injection section, and an SiO2 oxide layer separates the N well and the poly-silicon layer; another poly-silicon layer covers the surface of the P well between the second N+ injection section and the third N+ injection section and the SiO2 oxide layer separates P well and the poly-silicon layer. The trigger voltage provided by the silicon controlled rectifier embedded in the inverter is adjustable, the whole inverter embedded into an SCR without extra increasing the area.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a thyristor embedded in an inverter. Background technique [0002] Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating, and the whole process takes about 100ns. In addition, hundreds or even thousands of volts of high voltage will be generated when the integrated circuit is discharged, which will break through the gate oxide layer of the input stage in the integrated circuit. As the size of MOS transistors in integrated circuits is getting smaller and smaller, the thickness of the gate oxide layer is also getting thinner. Under this trend, high-performance electrostatic protection circuits are used to discharge electrostatic discharge charges to protect the gate. It is essential that the oxide layer is not damaged. [0003] Th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/04H01L27/02H01L23/60
Inventor 黄大海崔强霍明旭杜晓阳丁扣宝董树荣韩雁
Owner ZHEJIANG UNIV