An irregular topology structure generation method for chip network

A technology of on-chip network and topology structure, applied in the field of on-chip interconnection network design

Inactive Publication Date: 2008-09-17
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At present, a problem that has not been well resolved in the research of irregular topology is the design automation pro...

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  • An irregular topology structure generation method for chip network
  • An irregular topology structure generation method for chip network
  • An irregular topology structure generation method for chip network

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Embodiment Construction

[0022] Before describing the specific implementation, we first define five concepts: 1) All the nodes constituting the set A are called elements of the set A. 2) If there are common elements in the two sets, it is said that the two sets have an intersection. 3) If all elements in set B belong to set A and there are elements in A that do not belong to B, then set A is said to contain set B, expressed as B ⋐ A ; Otherwise, it is said that set A does not contain set B, expressed as B ⊂⃒ A . 4) The sum of the traffic between each node in a set and each node outside the set is called the external traffic of the set. 5) For edge routers, the ports connected to the nodes of the directed communication graph are called local ports, and other ports are called network ports. An edge router can have multiple local ports but only one network port. Assuming that the number of nodes in a...

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Abstract

An irregular topology generating method for a network-on-chip is disclosed, belonging the design field of the Internet-on-chip, characterized in that the method comprises the following steps of: dividing nodes in a communication diagram that describes the application of the network-on-chip into a plurality of sets; forming new nodes by using an edge router to connect all the nodes in each set, in order to form the new directional communication diagram; performing integrated division to the new directional communication diagram until a new set is unable to form or the number of the nodes is less than or equal to 5; then determining the number of core network routers and generating the core network according to the number of the nodes in the finally-formed communication diagram; simplifying the network by reducing the redundant edge routers. The invention has the characteristics of small area and low consumption in communication power on condition of meeting the communication demands of specific application.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the field of on-chip interconnection network design. Background technique [0002] Integrated circuits have been advancing in accordance with Moore's Law. The number of IP (Intellectual Property) cores integrated in a single chip is increasing. The traditional bus-based on-chip interconnect structure has shown outstanding performance in terms of bandwidth, power consumption, reliability, and scalability. Increasingly, on-chip communication has replaced computation as the bottleneck in IC design. Network-on-Chip (NoC), as a key technology in the field of integrated circuit design, is used to solve the problem of on-chip interconnection caused by the increase in chip size. The network on chip is mainly composed of routers, network interfaces and physical links. [0003] Topology is a hot issue in the research of network-on-chip. The research in this area can be divided in...

Claims

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Application Information

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IPC IPC(8): H04L12/02H04L12/56G06F13/42H04L12/801
CPCY02B60/1228Y02B60/1235Y02B60/33Y02D10/00Y02D30/50
Inventor 林世俊曾烈光金德鹏苏厉苏海波陈雪
Owner TSINGHUA UNIV
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