Method of manufacturing laminated lead frame and laminated lead frame produced by the method
A technology for stacking leads and lead frames, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of increased quality or accuracy required for fixtures, difficulty in transporting stacked lead frames, and difficulty in removing stacked lead frames. Subsequent conveying processing, facilitating subsequent processing, the effect of eliminating irregularities
Inactive Publication Date: 2008-10-01
MITSUI HIGH TEC INC
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Problems solved by technology
In the manufacturing process of the lead frame single board, the positioning hole obtained after bonding is narrowed by the slight misalignment of the lead frame single board, etc., and galling is generated in the pin, which is in the laminated lead frame. difficult to remove
These cause deformation or defects in the laminated lead frame
[0021] Sometimes, it also arises that the specifications set by the customer cause difficulties in forming positioning holes at desired positions on the side beams of the laminated lead frame because of restrictions, such as difficulties in transporting the laminated lead frame by using, for example, suction pads
[0022] In addition, when registering the lead frame single board and the completed laminated lead frame by using the positioning holes, it is necessary to relate to the position of the positioning pins, the distance between the positioning pins (or unit lead frames) of adjacent lead frames, and the lead frame Accuracy related to the external shape of the veneer, etc., which leads to an increase in the required mass or accuracy of the fixture, etc., and an accompanying increase in cost
Method used
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Embodiment Construction
[0068] In order to understand the present invention, a first embodiment of the present invention is described next by referring to the drawings.
[0069] 1 is a perspective view of a laminated lead frame to which a laminated lead frame manufacturing method according to a first embodiment of the present invention is applied; FIG. 2 is a descriptive view of the method; FIGS. view; and Figure 6A with 6B is a descriptive view of the method.
[0070] 1 and 2 show a method for manufacturing a laminated lead frame according to a first embodiment of the present invention. The lead 10 forming part of the upper lead frame single board and the lead 11 forming part of the lower lead frame single board are bonded together. A protruding portion 12 is created on each upper surface of the lower lead 11 .
[0071] The bottom surface (assuming a flat shape) of the upper lead 10 is coated with Ag-plating 13, which is an example of rare metal plating, and the upper surface of the protrusion 1...
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A method for manufacturing a laminated lead frame in which each lead frame unit plate to be laminated can be bonded surely with a relatively small load. A laminated lead frame is also provided. In the method for manufacturing a lead frame by laminating and bonding a plurality of lead frame unit plates (10, 11) subjected to predetermined shaping, a plurality of protrusions (12) are formed on one of the opposing surfaces of a pair of upper and lower lead frame unit plates (10, 11) and the opposing lead frame unit plates (11, 12) are bonded together through the protrusions (12).
Description
Background technique [0001] The present invention relates to a laminated leadframe for a semiconductor device such as an IC, and more particularly, to a laminated leadframe formed by laminating a plurality of thin plates and a method of manufacturing the same. [0002] In the field of QFN (Quad Flat Non-leaded) semiconductor devices, SON (Small Outline Non-leaded) with reduced lead pitch (inner lead) has been proposed in order to achieve thickness reduction. -leaded)) semiconductor devices, etc. There is a tendency to further reduce the thickness of the lead frame. However, when the thickness of the lead frame is reduced, the lead frame is liable to be twisted during a conveyance process or a subsequent assembly process, thus causing a failure, which in turn leads to a decrease in productivity. [0003] In the related art QFN semiconductor device or the related art SON semiconductor device, only the external contact terminals are exposed outside the sealing resin portion of ...
Claims
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Login to View More IPC IPC(8): H01L23/50
CPCH01L2924/0002
Inventor 松永清三村真也塩山隆雄
Owner MITSUI HIGH TEC INC