Analog IC having test arrangement and test method for such an IC

A technology for testing circuits and integrated circuits, which is applied in the direction of measuring electricity, measuring electrical variables, digital circuit testing, etc., and can solve problems such as increasing the total area

Inactive Publication Date: 2008-10-29
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this test circuit is that it requires a dedicated amplifier to selectively power the core, which significantly increases the total area of ​​the IC

Method used

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  • Analog IC having test arrangement and test method for such an IC
  • Analog IC having test arrangement and test method for such an IC
  • Analog IC having test arrangement and test method for such an IC

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Embodiment Construction

[0025] It should be understood that the drawings are merely schematic and not drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings and detailed description of the drawings to refer to the same or like parts. Furthermore, it should be understood that the various aspects of the invention shown in the various drawings and described in the detailed description thereof have been shown separately for the sake of clarity only; , you can combine them.

[0026] Figure 1 shows an IC with analog stages 10a-c. The analog stages 10a-c are conductively coupled via their respective branches 20a-c and 21a-c to a power supply line 20 for supplying a supply voltage to the stages 10a-c, as well as a common signal path 12. In Figure 1, the voltages on the internal nodes of the analog stages 10a-c are biased to appropriate values ​​by the biasing infrastructure. It is emphasized that different types of biasing (e.g., voltage-based biasin...

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PUM

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Abstract

An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.

Description

technical field [0001] The present invention relates to an integrated circuit (IC) comprising a plurality of analog stages, each of which is conductively coupled to a power supply and to each other via signal paths; and to a test circuit for testing the plurality of analog stages . [0002] The invention also relates to a test method for such an IC, and an IC test circuit comprising such an IC. Background technique [0003] Currently, IC testing is an important and integral part of the IC manufacturing process. IC testing plays an important role in improving the manufacturing process by detecting defects in the manufacturing process. Furthermore, IC testing significantly prevents defective ICs from being sold to the IC manufacturer's customers. The increasing complexity and modularity of ICs, such as System-on-Chip (SoC), has led to the development of new test techniques for digital ICs, such as the recently agreed SoC test standard IEEE1500, where the Various modules or...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185G01R31/317
CPCG01R31/3167G01R31/31721G01R31/318536G01R31/318575G01R31/28
Inventor 阿米尔·齐亚约亨德里克·J·贝戈弗尔德罗杰·F·舒特尔特乔斯·德·热苏斯·皮内达·德·于瓦兹
Owner NXP BV
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