IC testing methods and apparatus

Abstract

A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0]...wpi[N-1]) and respective parallel outputs (wpo[0]...wpo[N-1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.

Description

technical field [0001] The present invention generally relates to semiconductor integrated circuit testing, and in particular relates to a core testing method and equipment. Background technique [0002] One conventional testing technique used in the testing of semiconductor integrated circuits (ICs) is the scan testing technique. The technique essentially involves applying a test pattern (called a "vector") to the pins of a device package and monitoring the output response for a specific time, depending on the device's clock speed. A set of test vectors is used to enable the behavior of the device under test to be determined. These vectors are designed to be able to detect manufacturing defects in the device. [0003] As the number of transistors used in integrated circuits increases, the ability to reuse integrated circuit designs becomes increasingly important. An important issue with reusing design functionality (called "cores") is the ability to test these cores with...

AI Technical Summary

Problems solved by technology

A problem with this approach is that different bypass configurations must be tested for proper functioning as part of the overall testing process

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