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Processor and method for processing lock-based transaction

A processor and transaction technology, applied in the direction of electrical digital data processing, instruments, multi-programming devices, etc., can solve problems such as performance degradation and achieve efficient utilization

Inactive Publication Date: 2008-11-19
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If an atomic operation of a processing core has to block the global bus / network, this can lead to severe performance degradation

Method used

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  • Processor and method for processing lock-based transaction
  • Processor and method for processing lock-based transaction
  • Processor and method for processing lock-based transaction

Examples

Experimental program
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Embodiment Construction

[0022] In the following description, reference will be made to figure 1 The structure of the unit processor is shown to describe the embodiment of the present invention. However, those skilled in the art understand that figure 1 The details of the cell processors shown are provided for the purpose of illustrating the invention only and should not be construed as limiting the invention.

[0023] In addition, since the core mechanism of the signal light is similar to that of the phase lock, but there are differences in application, if the lock can be realized, the signal light can also be realized naturally, so the following only describes the present invention for the lock mechanism.

[0024] figure 2 The structure of a multi-core processor 10 with a fast lock mechanism based on an embodiment of the present invention is shown. like figure 2 As shown, the processor 10 includes an address arbiter and lock controller (AALC) 101 , a plurality of processing units PU 102 , 103 ...

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Abstract

Disclosed is a processor, which comprises at least a processing core, a switching device and a lock controller; wherein, each processing core is configured with a function corresponding to a specific instruction to submit a lock transaction request corresponding to the specific instruction to an address arbiter; the lock transaction request comprises a lock variable address stated on an address bus; the switching device is connected with the address arbiter and the lock controller respectively and used to identify the lock transaction request and inform the lock controller of the lock transaction request; the lock controller is used to respond to the lock transaction request, process the lock transaction and inform the processing core which submits the request of the processing results.

Description

technical field [0001] The invention generally relates to a lock mechanism of a shared memory in a multi-core processor, in particular to a lock mechanism of a shared memory based on an address arbiter in a multi-core processor. Background technique [0002] With the continuous progress of semiconductor technology, multi-core processors (such as cell processors CellProcessor) have been rapidly popularized. Multithreaded programs running on cores in a multicore processor must control concurrent access to shared memory regions. A common control method is to synchronize threads through locks / semaphores. Therefore lock / semaphore efficiency is a key factor for multi-threaded platforms. The lock implementation affects not only the overhead of synchronization operations, but also the blocking time of threads waiting for the lock to be released. This is critical for current processors that employ multi-core multi-threading as an important technique to fully utilize the small die ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46
CPCG06F9/526G06F2209/521G06F2209/522
Inventor 戈弋沈文博邵鹏别晓媛梁志勇
Owner INT BUSINESS MASCH CORP