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System and method for implementing data bit exchange

A technology of bit exchange and data bit, which is applied in the field of data bit exchange system, can solve the problems of uncertain delay, high cost, and data cannot be exchanged to multiple output time slots at the same time, so as to improve flexibility and cost-effective Effect

Inactive Publication Date: 2008-12-10
ZTE CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the implementation of this method is limited by the function of the dedicated switch chip itself. Therefore, the disadvantage of this method is that it can only complete the basic functions of switching by time slots, and the cost is relatively high.
This method needs to use up to three buffer frames, and the delay of data from input to output is uncertain. Due to the limitation of storage method design, the disadvantage of this method is that the data of a specific input time slot cannot be exchanged to multiple channels at the same time. output slots

Method used

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  • System and method for implementing data bit exchange
  • System and method for implementing data bit exchange
  • System and method for implementing data bit exchange

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Experimental program
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Effect test

Embodiment 1

[0124] This embodiment is in the normal working mode, Figure 5 The system structure based on the method embodiment one is based on Figure 5 structure, the implementation process of the method in this embodiment includes the following steps:

[0125] Step 201 , the control registration module 212 controls the switching of the working mode of the FPGA2 according to the configuration of the FPGA2 by the CPU1 .

[0126] Here, in the connection registration module 213, the 15th bit is set as the working mode selection bit. Setting this bit to 0 means that in the normal working mode, the connection mode is used to realize the operation of bit-exchanging the data input to FPGA2 and outputting it.

[0127] Step 202, four channels of 8.196MHz input data are input into the FPGA 2, and the input data processing unit 23 receives and buffers the input data according to the timing control signal provided by the control unit 22, and stores the input data in 4×2048 input DPRAM2311 for da...

Embodiment 2

[0137] In this embodiment, it is in the self-test working mode, Image 6 It is a schematic diagram of the system composition and structure based on the second method embodiment.

[0138] In this embodiment, the principles and operations of steps 301 to 305 are basically the same as those in the method embodiment 1. The difference is that in step 301 of this embodiment, the value of the 15th bit in the connection registration module 213 is set to 1, which means that in In the self-inspection working mode, the detection of FPGA2 is realized by means of messages, and the correctness of the operation of outputting the data input to FPGA2 is verified after bit swapping.

[0139] Then, when FPGA2 enters the self-test working mode, based on Image 6 structure, the implementation process of the method in this embodiment also includes the following steps:

[0140] Step 306, the output data processing unit 25 receives and buffers the four-way output data output from the connection uni...

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Abstract

The invention discloses a system of realizing data bit exchange, comprising a communicated processor (CPU) and a programmable logic device (FRGA); wherein, CPU is used for configuring FPGA; FPGA is used for obtaining the input data and outputting the input data after bit exchange according to the configuration of CPU. The invention further discloses a method of realizing the data bit exchange. Adopting the system and method in the invention tessellates to exchange the data according to bit and realizes the function of executing non-blocking exchange according to the bit in time slot; the invention is able to output any input bit on the appointed position of all needed outputting channel, which not only improves the flexibility of the data exchange, but also decreases the cost and has high cost performance.

Description

technical field [0001] The invention relates to data exchange technology in communication systems, in particular to a system and method for realizing data bit exchange. Background technique [0002] In the GSM communication system, with the rapid growth of users, the rapid expansion of the communication network scale is brought about. If things go on like this, it will inevitably lead to the problem that the communication network is not smooth; at the same time, in the process of expanding the communication network The investment is bound to involve the issue of saving investment costs. In order to solve the above problems, the existing communication network adopts half-rate voice communication technology, which can not only effectively solve the communication network congestion caused by sudden traffic, promote the year-on-year growth of traffic and business income; but also save the investment in wireless carrier frequency cost and improve resource utilization. The half-...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04L12/70
Inventor 徐妍罗军
Owner ZTE CORP