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Multithreading processor with each threading having multiple concurrent assembly line

A multi-threaded processor and pipeline technology, applied in the field of multi-threading and pipeline technology, can solve the problems of not supporting pipeline shift, not allowing multiple concurrent pipelines per thread, etc., to eliminate the need, high concurrency, and limit function. consumption effect

Inactive Publication Date: 2008-12-10
杉桥技术公司
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0012] However, these and other traditional approaches generally do not allow multiple concurrent pipelines per thread, nor do they support pipeline shifting

Method used

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  • Multithreading processor with each threading having multiple concurrent assembly line
  • Multithreading processor with each threading having multiple concurrent assembly line
  • Multithreading processor with each threading having multiple concurrent assembly line

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Embodiment Construction

[0028] The invention will be described in the context of an exemplary multithreaded processor. It is to be understood, however, that the invention does not require the particular arrangements shown and may be practiced using other types of digital data processors and associated processing circuits.

[0029] A given processor as described herein may be implemented in the form of one or more integrated circuits.

[0030] The present invention, in an illustrative embodiment, provides pipelining techniques suitable for use in multi-threaded processors. Using this technique, multiple instructions from multiple threads can be executed concurrently in an efficient manner. As will be described in more detail below, the illustrative embodiments provide concurrent execution using variable length execution pipelining, interleaved execution, and loop start execution while maintaining low power operation. The illustrative embodiments provide a higher degree of concurrency than achievable...

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Abstract

A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

Description

[0001] related application [0002] This application claims priority to US Provisional Application Serial No. 60 / 560,199, filed April 7, 2004, entitled "Processor Pipeline With Multithreaded Support," which is hereby incorporated by reference. [0003] This application is also related to US Patent Application Serial No. 10 / 841,261, entitled "Processor Reduction Unit for Accumulation of Multiple Operands With or Without Saturation," filed May 7, 2004, which is hereby incorporated by reference. technical field [0004] The present invention relates generally to the field of digital data processors, and more particularly to multithreading and pipelining techniques used in digital signal processors (DSP) or other types of digital data processors. Background technique [0005] Pipelining is a well-known processor implementation technique whereby multiple instructions are executed overlappingly. Conventional pipelining is described, for example, in "Computer Architecture: A Quant...

Claims

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Application Information

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IPC IPC(8): G06F15/00
Inventor 埃德姆·赫凯内克梅安·穆德基尔麦克尔·J.·舒尔特C.·约翰·格罗斯尼尔
Owner 杉桥技术公司
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