Clock receiver and correlative semiconductor memory module and emendation method

Abstract

The invention provides a clock receiver and related semiconductor memory module and correction method. The clock receiver comprises: a receiving units, for receiving a pair of complementary clock signal and produce a first clock signal; a correction unit, for detecting if there is a offset for crossing point of complementary clock signal and produce a result then regulating the first clock signal toggling. Crossing point offset resulting from inconsistent work cycle of clock signal VCLK / VCLK can be automatically corrected in the invention, thereby not influencing clock signal margin of internal circuit.

Description

technical field [0001] The present invention relates to semiconductor circuits, in particular to a clock receiver capable of automatically correcting phase shifts caused by inconsistencies in duty cycles of complementary clock signals. Background technique [0002] Generally speaking, a dynamic random access memory (DRAM) will use a receiver to receive a pair of complementary clock signals (such as: VCLK and / VCLK) from an external circuit, thereby generating a main clock signal (such as: MCLK) For internal circuit use. However, due to component mismatch, temperature or other factors, the duty cycles of the complementary clock signals (VCLK and / VCLK) will be inconsistent. [0003] Such as Figure 1A As shown, the duty cycle (duty cycle) of the clock VCLK is greater than the duty cycle of / VCLK, which will cause the two clock signals to generate cross points (cross points) CP3 and CP4 at time t1 and t3 respectively, but not at predetermined time t2 and t4 Intersection poin...

AI Technical Summary

Problems solved by technology

Therefore, the main clock signals MCLK and MCLK" will have a phase offset, which will affect the margin of the clock signal in the internal circuit.

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