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Circuit for preventing gating clock bur

A technology of gated clock and glitch, applied in electrical components, pulse processing, pulse technology, etc., can solve the problems of device failure packaging, chip reliability decline, electrical parameter drift, etc.

Inactive Publication Date: 2009-01-21
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

High power consumption will lead to the difficulty of chip heat dissipation design and the obvious increase of heat dissipation and packaging costs, and the reliability of the chip will also decrease significantly
Excessive temperature will cause drift of electrical parameters, failure of devices and failures related to packaging

Method used

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  • Circuit for preventing gating clock bur
  • Circuit for preventing gating clock bur
  • Circuit for preventing gating clock bur

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Experimental program
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Embodiment Construction

[0017] image 3 It is a circuit structure diagram of the present invention. The main purpose of the circuit of the present invention is to generate a gated clock signal that does not generate glitches.

[0018] At the same time, if two or more input signals of a combinational logic gate change state at the same time, since these input signals are generated through different paths, there is a slight time difference in the moment of their state change, which means This difference may cause some brief intermediate states on the output result signal, forming glitches. These glitches may produce some undesired results and propagate back through the circuit, causing errors in the functionality of the entire circuit. The present invention eliminates the competition between the two input signals of the gating enable signal and the input original clock by designing the timing sequence of the gating enable signal, and avoids inversion in two directions at the same moment, regardless o...

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Abstract

The present invention provides a circuit, which is used for preventing clock-gating glitches in the processing circuit of no-working clock in the design of low power consumption. The circuit adopts different clock edges to realize the clock switching control, effectively eliminates the potential competition in the clock switching process, and thus achieves the purpose of preventing the clock from generating the glitches in the gating process. No-working clock is generally applied in the design of low power consumption; the glitches appear in the switching process between the no-working clock and the novel provision of the clock; the circuit can be used for preventing the glitches in the switching process of clocks, and improving the stability and reliability of the circuit.

Description

technical field [0001] The present invention is mainly applied to circuits that need to stop clock processing for clocks during low power consumption design. It can be used in IC card chips, control chips used in portable consumer electronics, and other integrated circuit designs with low power consumption requirements. It can also be used to prevent high-speed chips from overheating, thereby improving product reliability. Background technique [0002] With the increasingly widespread application of portable consumer electronics products, the problem of power consumption is becoming more and more prominent. In order to meet users' demands for an updated experience, more and more functions are integrated into portable products, and the performance requirements for products are much higher than before. These features and performance improvements will consume more energy. In battery-powered portable products, in addition to functions and performance, battery life is also an i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/1252H03K5/1254
Inventor 郑晓光
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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