Memory system, abrasion equilibrium method and apparatus of non-volatile memory

A wear leveling and non-volatile technology, which is applied in the field of wear leveling and devices of memory systems and non-volatile memories, can solve problems such as system power-off, processing deviation, and erase count loss, and achieve system efficiency and wear Balanced effect with both effects

Active Publication Date: 2009-01-28
INTEL CORP
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Problems solved by technology

[0006] In order to solve the problem in the prior art that when the system is powered off when erasing a block, the erasure count of the block will also be lost, which will cause a deviation in the processing of the block in the next wear leveling, the present invention Provided are a memory system, a wear leveling method and device for a non-volatile memory

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  • Memory system, abrasion equilibrium method and apparatus of non-volatile memory
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Embodiment Construction

[0020] In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, the following specific examples will be described in detail with reference to the accompanying drawings.

[0021] In order to solve the problems in the prior art, the present invention proposes a wear leveling method, which can reflect the wear information of the block by using the erasure time stamp (time stamp) of the erasable block as the erasure mark, and in order to prevent Excessive use of wear leveling processing techniques results in reduced system performance, and the use of wear leveling seeds (wearleveling seed) to limit the number of times wear leveling occurs.

[0022] The first thing that needs to be explained is the concept of timestamp and wear leveling seed. The time stamp refers to the system time recorded on each erasable block in the EEPROM flash during the erasing operation. The time stamp can be stored in different locations, for exam...

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Abstract

The invention provides a wear-leveling method and a wear-leveling device for a memory system and a non-volatile memory, wherein the non-volatile memory comprises a plurality of data blocks and a linked list which is formed by the plurality of data blocks. The wear-leveling method comprises the following steps: firstly, a step of shift operation, namely the plurality of data blocks are arranged in order according to time values respectively corresponding to the plurality of data blocks and according to the time order of the time values, so as to form the linked list; and secondly, a step of erasure judgment, namely judgment is made whether to erase the plurality of data blocks, and when the plurality of data blocks are erased, corresponding data blocks are selected for erasure according to the time order of the time values of the plurality of data blocks in the linked list. The wear-leveling method and the wear-leveling device can simultaneously give attention to the system efficiency and the wear-leveling effect while really reflecting the service life of the erasable blocks in a system.

Description

technical field [0001] The invention relates to a wear leveling method and device applied to a storage medium management system, and is mainly applied to a medium management system of a large-capacity storage device. Background technique [0002] Non-volatile memory, such as Electrically Erasable Programmable Read-Only Memory EEPROM (Electrically Erasable Programmable Read-Only Memory), is a large-capacity storage medium with the physical characteristics of writing unit data and erasing entire block data. Consists of one or more memory cells, each of which stores one or more data bits. EEPROM is generally used in Plug & Play (Plug & Play) interface cards to store hardware setting data, and is also commonly used in "hardware locks" to prevent illegal copying of software. [0003] EEPROM generally performs erasing operations by dividing storage units into erasable blocks. However, due to the limitation of its own physical characteristics, there is a problem with the service l...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06
CPCG06F2212/7211G06F12/06G06F12/0246
Inventor 李榕金跃峰王利
Owner INTEL CORP
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