Light doping section, source/drain section forming method and membrane graphic method

Abstract

A method for forming a lightly doped region comprises the following steps: forming a grid electrode on a semiconductor substrate; cleaning the semiconductor substrate, on which the grid electrode is formed; carrying out heat treatment to the cleaned semiconductor substrate; forming a patterned resist etchant layer on the semiconductor substrate which is subjected to heat treatment, wherein the patterned resist etchant layer covers a part of the semiconductor substrate to expose the surface of a lightly doped region of the semiconductor substrate; and carrying out an ion implantation operationwith the patterned resist etchant layer and the grid electrode as a mask. The invention also provides a method for forming a source / drain region and a film patterning method, which both can optimize the patterning effect of the resist etchant layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a lightly doped region, a method for forming a source / drain region and a method for patterning a film layer. Background technique [0002] The lightly doped region includes a lightly doped drain (LDD) region and a pocket ion implantation region, and the lightly doped region is used to define a source-drain extension region of the MOS device. The LDD impurity is located below the gate and close to the edge of the channel region, and the Pocket impurity is located below the LDD region and close to the edge of the channel region, both of which provide impurity concentration gradients for the source and drain regions. [0003] Usually ion implantation is used to form the lightly doped region. Ion implantation is a standard technique for introducing conductivity-altering dopant materials into semiconductor substrates. In the ion implantation system, the required ...

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Problems solved by technology

However, it has been found in actual production that when the dimensional interval between the resist layer and the gate is small, the size of the exposed area usually deviates from the design value, that is, there are unremoved deposits in the exposed area, and in severe cases ,like Figure 4 As shown, a bridging (bridge) defect 32 is even formed between the resist layer and the gate, which affects the subsequent ion implantation operation.

However, in actual production, it has been found that when the above-mentioned method is used to remove the deposit forming a bridge between the resist layer and the gate, the removal effect is limited, and a plasma etching process needs to be added, which not only complicates the process, but also easily causes the gate surface damage

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