Stacked 1t-n memory cell structure

Abstract

This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a ''Z'' axis direction.

Description

[0001] This application is a continuation-in-part of US Patent Application 10 / 146,113, filed May 16, 2002, entitled "IT-nMTJ MRAM STRUCTURE," which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates to memory devices using arrays of stacked memory cells, including but not limited to non-volatile and semi-volatile programmable resistive memory cells such as MRAM and PCRAM, and in particular to read circuits for stacked memory cells. Background technique [0003] Integrated circuit designers have always sought the ideal semiconductor memory: a random-access device that can be written to or read instantly, is nonvolatile, can be modified infinitely, and consumes little power. Emerging technologies gradually provide these advantages. Some non-volatile or semi-volatile memory technologies include Magnetoresistive Random Access Memory (MRAM), Programmable Conductive Random Access Memory (Programmable Conductive Random Access...

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Problems solved by technology

Also, 1T-1Cell arrays are faster, but necessarily cannot be as densely integrated compared to crosspoint arrays because of the additional spacing required to provide a 1:1 ratio of access transistors to memory cells

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