Semiconductor memory device

Abstract

A semiconductor memory device includes a first active region formed having a first portion extending laterally and second portion extendedly vertically upward from a central portion of the first portion; a second active region formed spaced from the first active region, the second active region having a third portion extending laterally, fourth and fifth portions extending vertically downwardly at distal end portions of the third portion, and a sixth portion extending vertically downwardly at a central portion of the third portion; a first gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a second gate formed extending vertically and overlapping the first portion of the first active region and the third portion of the second active regions; a third gate formed extending in a direction perpendicular to the first and second gates and overlapping of the fourth and fifth portions of the second active region; and a plurality of contacts spaced apart predetermined distances from the gates.

Description

[0001] References to related applications [0002] This application claims priority under 35 US.C. §119 to Korean Patent Application No. 10-2007-0097297 filed September 27, 2007, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates to semiconductor memory devices and devices. Background technique [0004] The cell array scheme of a semiconductor memory device is an important technology for determining device specifications together with the structure and process conditions of the semiconductor layer. A semiconductor memory device of such a cell array scheme has a stacked gate structure, and shares a line contact with electrode lines in a plurality of cells, thereby enabling high integration. Furthermore, since layers of contacts and electrode lines can be connected in parallel, high functionality of the device can be implemented. [0005] However, the semiconductor memory device of the cell array scheme h...

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Problems solved by technology

[0005] However, the semiconductor memory device of the cell array scheme has the following problems: the wiring density becomes high, so it is difficult to ensure accurate process margin so that the yield rate deteriorates

In particular, in the case where a sufficient process margin cannot be ensured in terms of the distance between the contact and the gate line, the yield rate may be greatly deteriorated

However, in this regard, studies on process tolerances are insufficient, e.g. probe testing cannot be performed

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