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Multi-layer electrode and cross point memory array

A memory and cross-point technology, applied in the field of multi-layer electrodes, can solve the problems of slow operation speed and low integration density of flash memory devices

Inactive Publication Date: 2013-01-30
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, flash memory devices have lower integration density and slower operating speed compared to DRAM

Method used

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  • Multi-layer electrode and cross point memory array
  • Multi-layer electrode and cross point memory array
  • Multi-layer electrode and cross point memory array

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] Hereinafter, example embodiments will be described in detail by explaining example embodiments with reference to the accompanying drawings. In the drawings, the thickness and width of layers or regions are exaggerated for clarity.

[0022] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like reference numerals refer to like elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, compo...

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Abstract

A cross point memory array is provided to minimize a voltage drop by including an electrode structure having a multilayer structure. A first electrode(21) has a double layer structure of a first conductive layer(21a) and a second conductive layer(21b). A plurality of first laminate structures(S1) is formed on a top of the second conductive layer. A second electrode(25) intersects with the first electrode, and is formed on a top of the first laminate structure. A current(C1) supplied to a first memory resistor(22) of the first laminate structure is mainly delivered through the first conductive layer. The first electrode minimizes a voltage drop by a double layer structure laminated of the first conductive layer and the second conductive layer.

Description

technical field [0001] Example embodiments relate to a multilayer electrode, a memory device, and methods of manufacturing the same. Other example embodiments relate to a multilayer electrode, a cross-point resistive memory array, and methods of manufacturing the same. Background technique [0002] A semiconductor memory device may include a plurality of memory cells connected in a circuit. In a dynamic random access memory (DRAM), which is an example of a conventional semiconductor memory device, a unit memory cell may include a switch and a capacitor. DRAM can have increased integration density and faster operating speed. However, DRAM loses all stored data when the power is turned off. In contrast, an example of a nonvolatile memory device that can retain stored data even when the power is turned off may be a flash memory device. However, flash memory devices have lower integration density and slower operating speeds than DRAMs. [0003] Examples of non-volatile memo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/24H01L45/00G11C16/02
CPCG11C13/0004H10B63/20H10N70/231H10N70/011
Inventor 李昌范朴永洙李明宰斯蒂法诺维奇·詹瑞克金起焕
Owner SAMSUNG ELECTRONICS CO LTD